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    ROW HAMMER REFRESH COMMAND
    4.
    发明申请
    ROW HAMMER REFRESH COMMAND 审中-公开

    公开(公告)号：US20170076779A1

    公开(公告)日：2017-03-16

    申请号：US15363399

    申请日：2016-11-29

    Applicant: Intel Corporation

    Inventor： Kuljit S. BAINS ,  John B. HALBERT ,  Christopher P. MOZAK ,  Theodore Z. SCHOENBORN ,  Zvika GREENFIELD

    IPC: G11C11/4091 ,  G06F3/06 ,  G11C11/406

    CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

    Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

    Abstract translation: 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中重复访问时，物理上相邻的行（“受害者”行）可能会遭遇数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

    ASYMMETRICAL MEMORY MANAGEMENT
    7.
    发明申请
    ASYMMETRICAL MEMORY MANAGEMENT 审中-公开

    公开(公告)号：US20170300415A1

    公开(公告)日：2017-10-19

    申请号：US15442470

    申请日：2017-02-24

    Applicant: Intel Corporation

    Inventor： Nadav BONEN ,  Zvika GREENFIELD ,  Randy Osborne

    IPC: G06F12/08 ,  G06F13/16

    Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

    APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY
    8.
    发明申请
    APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY 审中-公开

    公开(公告)号：US20200226066A1

    公开(公告)日：2020-07-16

    申请号：US16833337

    申请日：2020-03-27

    Applicant: Intel Corporation

    Inventor： Eran SHIFER ,  Zeshan A. CHISHTI ,  Sanjay K. KUMAR ,  Zvika GREENFIELD ,  Philip LANTZ ,  Eshel SERLIN ,  Asaf RUBINSTEIN ,  Robert J. ROYER, JR.

    IPC: G06F12/0811 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/02 ,  G06F11/30 ,  G06F1/30

    Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.

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