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1.发明授权公开(公告)号：US12135886B2
公开(公告)日：2024-11-05
申请号：US18380608
申请日：2023-10-16
Applicant: Imagination Technologies Limited
Inventor： Ian King
IPC: G06F3/06
Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.
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公开(公告)号：US11915358B2
公开(公告)日：2024-02-27
申请号：US17584808
申请日：2022-01-26
Applicant: Imagination Technologies Limited
Inventor： Jamie Broome , Ian King
CPC classification number: G06T15/005 , G06T1/20 , G06T17/10 , G06T17/20
Abstract: A method and system for performing safety-critical rendering of a frame in a tile based graphics processing system. Geometry data for the frame is received, including data defining a plurality of primitives representing a plurality of objects in the frame. A definition of a region in the frame is received, the region being associated with one or more primitives among the plurality of primitives. Verification data is received that associates one or more primitives with the region in the frame. The frame is rendered using the geometry data and the rendering of the frame is controlled using the verification data, so that the rendering excludes, from the frame outside the region, the primitives identified by the verification data.
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公开(公告)号：US20230410243A1
公开(公告)日：2023-12-21
申请号：US18127579
申请日：2023-03-28
Applicant: Imagination Technologies Limited
Inventor： Michael John Livesley , Ian King
Abstract: A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core of the plurality of cores and assigns a second subset of the image rendering tasks to a second core of the plurality of cores. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications.
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4.发明授权公开(公告)号：US11789623B2
公开(公告)日：2023-10-17
申请号：US17318981
申请日：2021-05-12
Applicant: Imagination Technologies Limited
Inventor： Ian King
IPC: G06F3/06
CPC classification number: G06F3/0631 , G06F3/0604 , G06F3/067 , G06F3/0644 , G06F3/0659 , G06F3/0665
Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.
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公开(公告)号：US20230120307A1
公开(公告)日：2023-04-20
申请号：US17953821
申请日：2022-09-27
Applicant: Imagination Technologies Limited
Inventor： Michael John Livesley , Ian King , Alistair Goudie
Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.
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Patent Agency Ranking
公开(公告)号：US20230094013A1
公开(公告)日：2023-03-30
申请号：US17954511
申请日：2022-09-28
Applicant: Imagination Technologies Limited
Inventor： Michael John Livesley , Ian King , Alistair Goudie
Abstract: A processor includes a blocking circuit between an upstream section and a downstream section of a hardware pipeline, and control circuitry which triggers the upstream section to process an upstream phase of a first task, with the blocking circuit in an open state whereby first data from the processing of the upstream phase of the first task passes through from the upstream section to be processed in a downstream phase of the first task. In response to detecting that the upstream section has finished processing the upstream phase of the first task, the control circuitry triggers the upstream section to start processing a second task while the downstream section is still processing the downstream phase of the first task, and switches the blocking circuit to a closed state blocking second data from the processing of the upstream phase of the second task passing to the downstream section.
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公开(公告)号：US20220254088A1
公开(公告)日：2022-08-11
申请号：US17584979
申请日：2022-01-26
Applicant: Imagination Technologies Limited
Inventor： Jamie Broome , Ian King
Abstract: A method and system for performing safety-critical rendering of a frame in a tile based graphics processing system. Geometry data for the frame is received, including data defining a plurality of primitives representing a plurality of objects in the frame. A definition of a region in the frame is received, the region being associated with one or more primitives among the plurality of primitives. Verification data is received that associates one or more primitives with the region in the frame. The frame is rendered using the geometry data and the rendering of the frame is controlled using the verification data, so that the rendering excludes, from the frame outside the region, the primitives identified by the verification data.
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公开(公告)号：US12026828B2
公开(公告)日：2024-07-02
申请号：US17744426
申请日：2022-05-13
Applicant: Imagination Technologies Limited
Inventor： Peter Malcolm Lacey , Simon Fenney , Tobias Hector , Ian King
CPC classification number: G06T15/503 , G06F9/382 , G06T1/20 , G06T15/005 , G06T15/80 , G06T17/10 , G06T17/20 , G06T2200/28
Abstract: Implementations of blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.
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公开(公告)号：US11934257B2
公开(公告)日：2024-03-19
申请号：US17548043
申请日：2021-12-10
Applicant: Imagination Technologies Limited
Inventor： Ian King , Donald Scorgie
CPC classification number: G06F11/079 , G06F9/5038 , G06F11/073 , G06F12/023 , G06F2212/1041
Abstract: A method of processing an input task in a processing system involves duplicating the input task so as to form a first task and a second task; allocating memory including a first block of memory configured to store read-write data to be accessed during the processing of the first task; a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing the first task and the second task at processing logic of the processing system so as to, respectively, generate first and second outputs.
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公开(公告)号：US20240036995A1
公开(公告)日：2024-02-01
申请号：US18377723
申请日：2023-10-06
Applicant: Imagination Technologies Limited
Inventor： Damien McNamara , Jamie Broome , Ian King , Wei Shao , Mario Sopena Novales , Dilip Bansal
CPC classification number: G06F11/1633 , G06F9/5027 , G06T1/20 , G06F2201/82
Abstract: A graphics processing system includes a plurality of processing units, wherein the graphics processing system is configured to process a task first and second times at the plurality of processing units. Data identifying which processing unit of the plurality of processing units the task has been allocated to is consulted on allocating the task to a processing unit for processing for a second time, and, in response, the task is allocated for processing for the second time to any processing unit of the plurality of processing units other than the processing unit to which the task was allocated for processing for a first time.
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