公开(公告)号：US20250102740A1

公开(公告)日：2025-03-27

申请号：US18373851

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Harel FRISH ,  Hari MAHALINGAM ,  Saeed FATHOLOLOUMI ,  Shane YERKES ,  John HECK ,  Wei QIAN

IPC: G02B6/36

Abstract: A device comprising a silicon substrate and a waveguide on the silicon substrate. A groove is in the substrate, the groove having a sloped rear wall adjacent to the waveguide. A trench is in the substrate, the trench along a second direction generally orthogonal to the first direction across the sloped rear wall, the trench having a vertical wall at an intersection with the sloped rear wall. An optical fiber in the groove with one end of the optical fiber abutting the vertical wall.

公开(公告)号：US20240103304A1

公开(公告)日：2024-03-28

申请号：US17954286

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  John HECK ,  Ling LIAO ,  Mengyuan HUANG ,  Wilfred GOMES ,  Pushkar RANADE ,  Abhishek Anil SHARMA

IPC: G02F1/025

CPC classification number: G02F1/025

Abstract: Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.

公开(公告)号：US20240103216A1

公开(公告)日：2024-03-28

申请号：US17954292

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  John HECK ,  Ling LIAO ,  Mengyuan HUANG ,  Wilfred GOMES ,  Pushkar RANADE ,  Abhishek Anil SHARMA

IPC: G02B6/12 ,  H01L25/16

CPC classification number: G02B6/12004 ,  H01L25/167

Abstract: Embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. In an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. In an embodiment, a waveguide is provided through the substrate. In an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.

公开(公告)号：US20210074866A1

公开(公告)日：2021-03-11

申请号：US16562889

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Priyanka DOBRIYAL ,  Ankur AGRAWAL ,  Susheel JADHAV ,  Quan TRAN ,  Raghuram NARAYAN ,  Raiyomand ASPANDIAR ,  Kenneth BROWN ,  John HECK

IPC: H01L31/0232 ,  G02B3/00 ,  H01L31/0216 ,  H01L31/02 ,  H01L25/16 ,  H01L23/538 ,  H01L31/18 ,  G02B1/11 ,  G02B6/42

Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment the optoelectronic system comprises a board, and a carrier attached to the board. In an embodiment, a first die is on the carrier. In an embodiment, the first die is a photonics die, and a surface of the first die is covered by an optically transparent layer.

公开(公告)号：US20180156661A1

公开(公告)日：2018-06-07

申请号：US15786575

申请日：2017-10-17

Applicant: Intel Corporation

Inventor： Jonathan K. DOYLEND ,  David N. HUTCHISON ,  John HECK ,  Haisheng RONG ,  Daniel GRODENSKY ,  David ARBEL ,  Israel PETRONIUS

IPC: G01J1/42 ,  G01S7/481 ,  G01S17/10 ,  G02F1/29 ,  G01S17/42 ,  G01B11/22 ,  G01S17/88 ,  G01S7/484

CPC classification number: G01J1/4228 ,  G01B11/22 ,  G01S7/4813 ,  G01S7/4817 ,  G01S7/484 ,  G01S17/10 ,  G01S17/42 ,  G01S17/88 ,  G02F1/292

Abstract: An optical circuit includes solid state photonics. The optical circuit includes a phased array of solid state waveguides that perform beamsteering on an optical signal. The optical circuit includes a modulator to modulate a bit sequence onto the carrier frequency of the optical signal, and the beamsteered signal includes the modulated bit sequence. The optical circuit includes a photodetector to detect a reflection of the beamsteered optical signal. The optical circuit autocorrelates the reflection signal with the bit sequence to generate a processed signal.

公开(公告)号：US20240176167A1

公开(公告)日：2024-05-30

申请号：US18071246

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Tolga ACIKALIN ,  Harel FRISH ,  Sandeep GAAN ,  John HECK ,  Eric J. M. MORET ,  Suddhasattwa NAD ,  Haisheng RONG

IPC: G02F1/01 ,  G02B6/125

CPC classification number: G02F1/0113 ,  G02B6/125 ,  G02F1/0147 ,  G02B2006/12145

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core where the core comprises glass. In an embodiment, the package substrate further comprises an optical waveguide over the core, and an optical phase change material over the optical waveguide.

公开(公告)号：US20230185022A1

公开(公告)日：2023-06-15

申请号：US17549506

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： John HECK

IPC: G02B6/122 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/136

Abstract: Embodiments herein relate to systems, apparatuses, or processes for a silicon lens manufactured on a 110-oriented silicon wafer that includes highly accurate vertical alignment features on the edges of the silicon lens created using crystallographic etching. In embodiments, these vertical alignment features are revealed 111 planes in the silicon wafer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220084936A1

公开(公告)日：2022-03-17

申请号：US17024507

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Wei QIAN ,  Cung TRAN ,  Sungbong PARK ,  John HECK ,  Mark ISENBERGER ,  Seth SLAVIN ,  Mengyuan HUANG ,  Kelly MAGRUDER ,  Harel FRISH ,  Reece DEFREES ,  Zhi LI

IPC: H01L23/522 ,  H01L23/528

Abstract: Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.