公开(公告)号：US20170132004A1

公开(公告)日：2017-05-11

申请号：US15408632

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Michael W. Chynoweth ,  Peggy J. Irelan ,  Matthew C. Merten ,  Seung-Woo Kim ,  Laura A. Knauth ,  Stanislav Bratanov

IPC: G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30058 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3016 ,  G06F11/3409 ,  G06F11/3476 ,  G06F11/348 ,  G06F12/0875

Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.

公开(公告)号：US08782382B2

公开(公告)日：2014-07-15

申请号：US13786724

申请日：2013-03-06

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F9/38

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行单元和至少一个最后一个分支记录（LBR）寄存器，用于存储在程序执行期间所采取的分支的地址信息。 该寄存器还可以存储事务指示符以指示在事务存储器（TM）事务期间是否采取了分支。 该寄存器可以进一步存储中止指示符以指示分支是否由事务中止引起。 描述和要求保护其他实施例。

公开(公告)号：US10073719B2

公开(公告)日：2018-09-11

申请号：US15131099

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/52 ,  G06F11/34 ,  G06F11/36 ,  G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F11/14

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

公开(公告)号：US20170235638A1

公开(公告)日：2017-08-17

申请号：US15586898

申请日：2017-05-04

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Peggy J. Irelan ,  Konrad K. Lai ,  Martin G. Dixon

IPC: G06F11/14 ,  G06F13/42 ,  G06F13/16 ,  G06F11/34 ,  G06F9/30 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0862 ,  G06F11/30

CPC classification number: G06F9/3861 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F9/528 ,  G06F11/1407 ,  G06F11/1469 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/348 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/4282 ,  G06F15/80 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/62 ,  G06F2213/0026

Abstract: An example system for speculative execution event counter checkpointing and restoring may include a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores. The system may further include a memory controller to couple the symmetric cores to a system memory and a data communication interface to couple one or more of the cores to input/output devices. The system may further include event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters and one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The system may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The system may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The system may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.

公开(公告)号：US20170235579A1

公开(公告)日：2017-08-17

申请号：US15586636

申请日：2017-05-04

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Peggy J. Irelan ,  Konrad K. Lai ,  Martin G. Dixon

IPC: G06F9/38 ,  G06F9/46 ,  G06F12/0875 ,  G06F12/084 ,  G06F15/80 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F9/528 ,  G06F11/1407 ,  G06F11/1469 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/348 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/4282 ,  G06F15/80 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/62 ,  G06F2213/0026

Abstract: An example processor for speculative execution event counter checkpointing and restoring may include a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores. The processor may further include event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters and one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The processor may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The processor may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The processor may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.

公开(公告)号：US20160026464A1

公开(公告)日：2016-01-28

申请号：US14811552

申请日：2015-07-28

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Matthew C. Merten ,  Ronak Singhal ,  Hugh M. Caffrey

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30109 ,  G06F9/30112 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/88

Abstract: A processor includes one or more execution units to execute instructions, each having one or more elements in different element sizes using one or more registers in different register sizes. The processor further includes a counter configured to count a number of instructions performing predetermined types of operations executed by the one or more execution units. The processor further includes one or more registers to allow an external component to configure the counter to count a number of instructions associated with a combination of a register size and a element size (register/element size) and to retrieve a counter value produced by the counter.

Abstract translation: 处理器包括执行指令的一个或多个执行单元，每个执行单元具有使用不同寄存器大小的一个或多个寄存器的不同元件大小的一个或多个元件。 处理器还包括计数器，其被配置为对执行由一个或多个执行单元执行的预定类型的操作的多个指令进行计数。 处理器还包括一个或多个寄存器，以允许外部组件配置计数器以对与寄存器大小和元素大小（寄存器/元素大小）的组合相关联的多个指令进行计数，并且检索由 计数器。

公开(公告)号：US10261792B2

公开(公告)日：2019-04-16

申请号：US15408632

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Michael W. Chynoweth ,  Peggy J. Irelan ,  Matthew C. Merten ,  Seung-Woo Kim ,  Laura A. Knauth ,  Stanislav Bratanov

IPC: G06F9/30 ,  G06F11/34 ,  G06F12/0875

Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.

公开(公告)号：US20170235580A1

公开(公告)日：2017-08-17

申请号：US15586930

申请日：2017-05-04

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Peggy J. Irelan ,  Konrad K. Lai ,  Martin G. Dixon

IPC: G06F9/38 ,  G06F9/46 ,  G06F12/084 ,  G06F13/42 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3861 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F9/528 ,  G06F11/1407 ,  G06F11/1469 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/348 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/4282 ,  G06F15/80 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/62 ,  G06F2213/0026

Abstract: An example system for speculative execution event counter checkpointing and restoring may include a plurality of processors, a first interconnect to couple two or more of the plurality of processors, a second interconnect to couple one or more of the plurality of processors to one or more other system components, and a system memory coupled to one or more of the processors. At least one processor of the plurality of processors may include: a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores; and event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters; one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The processor may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The processor may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The processor may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.

公开(公告)号：US09733939B2

公开(公告)日：2017-08-15

申请号：US13631664

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Vijaykumar Balaram Kadgi ,  James D. Hadley ,  Avinash Sodani ,  Matthew C. Merten ,  Morris Marden ,  Joseph A. McMahon ,  Grace C. Lee ,  Laura A. Knauth ,  Robert S. Chappell ,  Fariborz Tabesh

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30105 ,  G06F9/384

Abstract: A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.

公开(公告)号：US20160232041A1

公开(公告)日：2016-08-11

申请号：US15131099

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F9/52 ,  G06F11/14 ,  G06F9/38

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行单元和至少一个最后一个分支记录（LBR）寄存器，用于存储在程序执行期间所采取的分支的地址信息。 该寄存器还可以存储事务指示符以指示在事务存储器（TM）事务期间是否采取了分支。 该寄存器可以进一步存储中止指示符以指示分支是否由事务中止引起。 描述和要求保护其他实施例。