公开(公告)号：US12218052B2

公开(公告)日：2025-02-04

申请号：US18384582

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US11874600B2

公开(公告)日：2024-01-16

申请号：US17712953

申请日：2022-04-04

Applicant: Intel Corporation

Inventor： Marie Krysak ,  James M. Blackwell ,  Robert L. Bristol ,  Florian Gstrein

IPC: G03F7/004 ,  G03F7/20 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: G03F7/0043 ,  G03F7/2004 ,  B82Y30/00 ,  B82Y40/00 ,  G03F7/0048

Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.

公开(公告)号：US11862463B2

公开(公告)日：2024-01-02

申请号：US17544684

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Marie Krysak ,  Florian Gstrein ,  Manish Chandhok

IPC: H01L21/033 ,  C01G27/02 ,  C01G19/02 ,  C01G23/04 ,  C01F7/02 ,  C01G25/02 ,  H01L21/02 ,  C01F7/00 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0332 ,  C01F7/00 ,  C01F7/02 ,  C01G19/02 ,  C01G23/04 ,  C01G25/02 ,  C01G27/02 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76897 ,  C01P2004/64

Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.

公开(公告)号：US11227766B2

公开(公告)日：2022-01-18

申请号：US16316990

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Marie Krysak ,  Florian Gstrein ,  Manish Chandhok

IPC: C01G27/02 ,  C01G19/02 ,  C01G23/04 ,  C01F7/02 ,  C01G25/02 ,  C01F7/00 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768

Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.

公开(公告)号：US12037434B2

公开(公告)日：2024-07-16

申请号：US17313932

申请日：2021-05-06

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US11984317B2

公开(公告)日：2024-05-14

申请号：US17308813

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Marie Krysak ,  James Blackwell ,  Lauren Doyle ,  Brian Zaccheo ,  Patrick Theofanis ,  Michael Robinson ,  Florian Gstrein

IPC: H01L21/027 ,  G03F7/004 ,  G03F7/20 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/0274 ,  G03F7/0042 ,  H01L21/76877 ,  H01L23/5226 ,  G03F7/2004

Abstract: Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.

公开(公告)号：US11955377B2

公开(公告)日：2024-04-09

申请号：US17568648

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Robert L Bristol ,  James M. Blackwell ,  Rami Hourani ,  Marie Krysak

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76825 ,  H01L21/76877 ,  H01L21/76897

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US11955343B2

公开(公告)日：2024-04-09

申请号：US17701367

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Marie Krysak ,  James M. Blackwell ,  Florian Gstrein ,  Kent N. Frasure

IPC: G03F7/039 ,  G03F7/004 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31144 ,  G03F7/0045 ,  G03F7/0392 ,  G03F7/203 ,  G03F7/38 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US11406972B2

公开(公告)日：2022-08-09

申请号：US15772839

申请日：2015-12-04

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  David J. Michalak ,  Jessica M. Torres ,  Marie Krysak ,  Jeffery D. Bielefeld

IPC: B01J37/08 ,  H01B3/46 ,  H01B3/22 ,  B01J21/02 ,  B01J31/02 ,  C08J3/24 ,  C08L83/16

Abstract: Catalysts for facilitating cross-linking of liquid precursors into solid dielectric materials are disclosed. Initially, catalysts are protected, either by coordination with other compounds or by conversion to an ionic salt. Protection prevents catalysts from facilitating cross-linking unless activated. A catalyst is activated upon receiving an excitation, e.g. thermal excitation by heating. Upon receiving an excitation, protection of a catalyst dissociates, decomposes, becomes neutralized, or is otherwise transformed to allow the catalyst to facilitate cross-linking of the precursors into solid dielectric materials. Methods for fabricating dielectric materials using such protected catalysts as well as devices comprising the resulting materials are also described. Dielectric materials comprising cross-linked cyclic carbosilane units having a ring structure including C and Si may be formed in this manner. Protected catalysts disclosed herein allow careful control of precursor cross-linking, resulting in higher quality dielectric materials that may be formed by coating techniques.

公开(公告)号：US11373950B2

公开(公告)日：2022-06-28

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.