公开(公告)号：US12282377B2

公开(公告)日：2025-04-22

申请号：US17358224

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Pritesh P. Shah ,  Suresh Chemudupati ,  Alexander Gendler ,  David Hunt ,  Christopher M. Macnamara ,  Ofer Nathan ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3287 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/50

Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

公开(公告)号：US08996895B2

公开(公告)日：2015-03-31

申请号：US14317239

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

IPC: G06F1/00 ,  G06F1/32 ,  G06F13/24 ,  G06F15/00

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

Abstract translation: 处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。 对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。 功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。

公开(公告)号：US20190102335A1

公开(公告)日：2019-04-04

申请号：US15721560

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Siang Lin Tan ,  Su Wei Lim ,  Ming Chew Lee ,  Ofer Nathan

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/20

Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

公开(公告)号：US20180059763A1

公开(公告)日：2018-03-01

申请号：US15250123

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J Ragland ,  Ofer Nathan ,  Nadav Shulman ,  Esfir Natanzon

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3296

Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

公开(公告)号：US10311000B2

公开(公告)日：2019-06-04

申请号：US15721560

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Siang Lin Tan ,  Su Wei Lim ,  Ming Chew Lee ,  Ofer Nathan

IPC: G06F13/20 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

公开(公告)号：US09660799B1

公开(公告)日：2017-05-23

申请号：US14950319

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC: G06F1/06 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US08806248B2

公开(公告)日：2014-08-12

申请号：US14041688

申请日：2013-09-30

Applicant: Intel Corporation

Inventor： Jose P. Allarey ,  Varghese George ,  Sanjeev S. Jahagirdar ,  Oren Lamdan ,  Ofer Nathan ,  Tomer Ziv

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

公开(公告)号：US20170149554A1

公开(公告)日：2017-05-25

申请号：US14950319

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US08769323B2

公开(公告)日：2014-07-01

申请号：US13788547

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Jose P. Allarey ,  Varghese George ,  Sanjeev Jahagirdar ,  Oren Lamdan ,  Ofer Nathan ,  Tomer Ziv

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

Abstract translation: 随着对多核处理器的进展，每个核心都不能容易地确定另一个模具相对于空闲或活动状态的状态。 讨论了在多芯片微处理器中利用接口在多个核心之间传输核心状态的提议。 因此，这通过允许基于利用每个核心状态来设置性能和频率的最佳设置来促进热管理。

公开(公告)号：US10095302B2

公开(公告)日：2018-10-09

申请号：US15250123

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J Ragland ,  Ofer Nathan ,  Nadav Shulman ,  Esfir Natanzon

IPC: G06F1/32

Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.