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公开(公告)号：US20230205244A1
公开(公告)日：2023-06-29
申请号：US17561109
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Anand Ramasundar , Cary Renzema , Fabrice Paillet , James Keith Hodgson , Po-Cheng Chen , Sergio Carlo Rodriguez , Harish K. Krishnamurthy , Jason Muhlestein
Abstract: An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.
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公开(公告)号：US20230168705A1
公开(公告)日：2023-06-01
申请号：US17540046
申请日：2021-12-01
Applicant: Intel Corporation
Inventor： Sergio Carlo Rodriguez , Cary D, Renzema , Amit K. Jain , Po-Cheng Chen , Fabrice Paillet , Anand Ramasundar , James Keith Hodgson
IPC: G05F1/577
CPC classification number: G05F1/577
Abstract: Embodiments herein relate to a feedback loop in a digital voltage regulator for controlling an output voltage. To avoid instability at light current loads, a gain of the loop is reduced as a power gate code indicates a reduced number of branches in set of current sources are enabled. In an example implementation, the code is classified into one range of a number of ranges, and the gain is set based on the one range. The gain can decrease each time the code enters a lower range, as indicated by the code crossing a threshold or predetermined value. For example, the gain can decrease by half each time the code enters a lower range.
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公开(公告)号：US11755048B2
公开(公告)日：2023-09-12
申请号：US17220802
申请日：2021-04-01
Applicant: Intel Corporation
Inventor： Sergio Carlo Rodriguez , Alexander Lyakhov , Gerhard Schrom , Keith Hodgson , Sarath S. Makala , Sidhanto Roy
CPC classification number: G05F1/652 , G05F1/44 , H02M3/157 , H02M1/0025 , H03M1/66
Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.
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公开(公告)号：US20210223811A1
公开(公告)日：2021-07-22
申请号：US17220802
申请日：2021-04-01
Applicant: Intel Corporation
Inventor： Sergio Carlo Rodriguez , Alexander Lyakhov , Gerhard Schrom , Keith Hodgson , Sarath S. Makala , Sidhanto Roy
Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.
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Patent Agency Ranking
公开(公告)号：US20230208437A1
公开(公告)日：2023-06-29
申请号：US17561246
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Sami Hyvonen , Fabrice Paillet , James Keith Hodgson , Anand Ramasundar , Cary Renzema , George Matthew , Sergio Carlo Rodriguez , Po-Cheng Chen , Sandeep Chilka , Bharadwaj Soundararajan
Abstract: A digitally selectable power gate with thermometer-encoded upper bits may provide solutions for problems digital power gate-based regulators. These solutions may include the use of a fully binary power gate, either in structure or by local decoding of binary control signal to an addressable row-based power gate. This provides improved performance over a row-based code rotation, which is intended to avoid instantaneous overheating of power gate devices but may not mitigate aging effects. Another solution includes ganging a primary DLVR and one or more secondaries. The primary DLVR may include a voltage sense and active controller, which may forward its PG code to secondary instances. Therm and current sensor rotation may be performed locally at the secondaries and a current monitor data may be rolled up from all ganged DLVRs.
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公开(公告)号：US10976764B2
公开(公告)日：2021-04-13
申请号：US16575259
申请日：2019-09-18
Applicant: Intel Corporation
Inventor： Sergio Carlo Rodriguez , Alexander Lyakhov , Gerhard Schrom , Keith Hodgson , Sarath S. Makala , Sidhanto Roy
Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.
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7.发明授权公开(公告)号：US11429173B2
公开(公告)日：2022-08-30
申请号：US16230440
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Chee Lim Nge , Amit Jain , Anant Deval , Nimrod Angel , Fabrice Paillet , Michael Zelikson , Sergio Carlo Rodriguez
IPC: G06F1/26 , G06F1/32 , G06F1/3206 , H02M3/158 , H02M1/08 , G06F1/20 , G06F1/3296 , H02M1/32 , G06F1/324 , H02M1/00 , H02M3/156
Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.
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公开(公告)号：US20210080987A1
公开(公告)日：2021-03-18
申请号：US16575259
申请日：2019-09-18
Applicant: Intel Corporation
Inventor： Sergio Carlo Rodriguez , Alexander Lyakhov , Gerhard Schrom , Keith Hodgson , Sarath S. Makala , Sidhanto Roy
Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.
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公开(公告)号：US10122265B1
公开(公告)日：2018-11-06
申请号：US15861604
申请日：2018-01-03
Applicant: Intel Corporation
Inventor： George E. Matthew , Gerhard Schrom , Alexander Lyakhov , Rachid E. Rayess , Anant S. Deval , Sergio Carlo Rodriguez , Pushkar Dixit
Abstract: An apparatus is provided which comprises: at least two switches in series between an input voltage node and a ground terminal; an inductor coupled between a mid-point of the at least two switches and an output terminal; a first circuitry to compare a current through the inductor with a threshold current, and to control one or both of the at least two switches, based at least in part on the comparison; and a second circuitry to randomly vary the threshold current over consecutive cycles of switching of the at least two switches.
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