公开(公告)号：US20240057256A1

公开(公告)日：2024-02-15

申请号：US18268867

申请日：2021-05-19

Applicant: JCET GROUP CO., LTD.

Inventor： Yaojian LIN ,  Chenye HE ,  Shuo LIU ,  Danfeng YANG ,  Li ZOU

IPC: H05K1/16 ,  H05K1/14 ,  H05K1/11 ,  H05K3/34 ,  H05K3/28 ,  H05K3/10

CPC classification number: H05K1/165 ,  H05K1/144 ,  H05K1/111 ,  H05K3/3457 ,  H05K3/284 ,  H05K3/103 ,  H05K2203/041 ,  H05K2201/0715 ,  H05K2201/0909

Abstract: The present invention provides a package structure with an inductor and a manufacturing method thereof, the inductor and the interconnection component are used as n second package module, and stacked with other components such as the first package module to form a stack-like package structure. The first package module is provided with other electronic elements. Then the first and second package modules can be synchronously subjected to package manufacturing, which improves the production efficiency. Additionally, the soldering balls with different heights are formed on the first faces of the interconnecting structural component and the inductive device by adjusting the consumption of soldering paste, which make the second faces of the inductor and the interconnection component are coplanar, then inductor with different heights can form a flat interconnecting plane, which makes the sequential process such as pasting and mounting can be conveniently performed. The process is simplified, and the reliability of the package structure is improved.

公开(公告)号：US20250062298A1

公开(公告)日：2025-02-20

申请号：US18792364

申请日：2024-08-01

Applicant: JCET Group Co., Ltd.

Inventor： Yaojian LIN ,  Yao LI ,  Danfeng YANG ,  Lei LV

IPC: H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/538

Abstract: The present disclosure relates to a package structure and a method for forming the same. The package structure includes: a plurality of second interconnect metal traces and bonding pads in a same plane; a plurality of first surface metal bumps and first interconnect metal traces disposed on the first surfaces of the second interconnect metal traces; a plurality of passive devices correspondingly mounted on top surfaces of the first surface metal bumps; a first molding layer encapsulating the passive devices, the first surface metal bumps, and the first interconnect metal traces, and covering the first surfaces of the bonding pads; a dielectric layer covering the second surfaces of the second interconnect metal traces and a bottom surface of the first molding layer; a first chip having wire bonding pads; and metal wires electrically connecting the wire bonding pads to the second surfaces of the bonding pads.

公开(公告)号：US20250062215A1

公开(公告)日：2025-02-20

申请号：US18800344

申请日：2024-08-12

Applicant: JCET Group Co., Ltd.

Inventor： Danfeng YANG ,  Yao LI ,  Lei LV ,  Songhua XU ,  Yaojian LIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16

Abstract: The present disclosure relates to a package structure and a method for forming the same. The package structure includes: a first surface and a second surface that are opposite, passive devices mounted on the first surface of the substrate; a first molding layer encapsulating the passive devices and covering the first surface of the substrate; a first chip comprising a back face and a functional face that are opposite; metal connection structures each comprising a horizontal metal strip and a vertical metal pin electrically connected to the horizontal metal strip; a second molding layer encapsulating the metal connection structures and the first chip and covering the second surface of the substrate; and first solder bumps on the exposed top surfaces of the external terminals.