公开(公告)号：US20030168255A1

公开(公告)日：2003-09-11

申请号：US10384658

申请日：2003-03-11

Applicant: LG ELECTRONICS INC.

Inventor： Dock-Heung Kim ,  Yong-Il Kim

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K3/4652 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/0097 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913

Abstract: A multi-layer printed circuit board on which insulation resin layers and circuit pattern layers are alternatively stacked to form multiple layers, including: an insulation resin layer; a circuit pattern formed at the upper surface of the insulation resin layer; a blind via hole formed penetrating the insulation resin layer and the circuit pattern; a plated layer formed at the upper surface of the circuit pattern, at the inner wall face and the bottom of the blind via hole; an inner lead bump pad formed at the surface of the plated layer which is exposed to the lower surface of the insulation resin layer; and an outer lead bump pad formed on the circuit pattern which is formed at the upper surface of the insulation resin layer, whereby the problem of defective attachment of a bump due to a void present in a blind via hole is eliminated.

公开(公告)号：US20040200726A1

公开(公告)日：2004-10-14

申请号：US10836219

申请日：2004-05-03

Applicant: LG Electronics Inc.

Inventor： Sung-Gue Lee ,  Yong-Il Kim

IPC: C25D005/02 ,  C25D007/12

CPC classification number: H05K3/243 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2203/0597 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: A method for forming bonding pads on a printed circuit board (PCB) with circuit patterns is provided. A plurality of copper patterns are formed on the PCB which are electrically connected to the circuit patterns, and a filler is filled between the copper patterns such that an upper surface of the copper pattern is exposed. A plating layer is then applied to the exposed upper surface of the copper patterns. Protrusion of the plating layer at a lower portion of a copper pattern is prevented, thus reducing an interval between the wire bonding pad(s) and potentially increasing the number of bonding pads which may be effectively formed on a given PCB.

Abstract translation: 提供了一种用于在具有电路图案的印刷电路板（PCB）上形成焊盘的方法。 在PCB上形成多个铜图形，其电连接到电路图案，并且填充物填充在铜图案之间，使得铜图案的上表面露出。 然后将镀层施加到铜图案的暴露的上表面。 防止在铜图案的下部的镀层的突出，从而减少引线键合焊盘之间的间隔并且潜在地增加可能在给定PCB上有效形成的焊盘的数量。

公开(公告)号：US20030089521A1

公开(公告)日：2003-05-15

申请号：US10291606

申请日：2002-11-12

Applicant: LG Electronics Inc.

Inventor： Sung-Gue Lee ,  Yong-Il Kim

IPC: H05K001/09 ,  H05K003/10

CPC classification number: H05K3/243 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2203/0597 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: Bonding pad(s) formed on a printed circuit board with circuit patterns. The bonding pad(s) include a plurality of copper patterns formed on the PCB and electrically connected to the circuit patterns, a filler filled between the copper patterns such that an upper surface of the copper pattern is exposed, and a plating layer applied at an upper surface of the copper patterns. An interval between wire bonding pad(s) is reduced by preventing a nickel plating layer and a gold plating layer from protruding at a lower portion of a copper pattern when they are formed on the copper patterns.

Abstract translation: 在印刷电路板上形成的具有电路图案的接合焊盘。 焊盘包括形成在PCB上并电连接到电路图案的多个铜图案，填充在铜图案之间的填充物，使得铜图案的上表面暴露，并且镀覆层 铜图案的上表面。 通过防止镀镍层和镀金层在铜图案上形成时在铜图案的下部突出，从而降低引线接合焊盘之间的间隔。