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1.发明申请公开(公告)号：US20180013442A1
公开(公告)日：2018-01-11
申请号：US15711177
申请日：2017-09-21
Applicant: Maxlinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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2.发明申请公开(公告)号：US20170346500A1
公开(公告)日：2017-11-30
申请号：US15674700
申请日：2017-08-11
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
CPC classification number: H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.
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3.发明授权Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) 有权用于异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统公开(公告)号：US09136859B2
公开(公告)日：2015-09-15
申请号：US14585656
申请日：2014-12-30
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中先占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
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4.发明授权Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) 有权用于异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统公开(公告)号：US08922415B2
公开(公告)日：2014-12-30
申请号：US13964043
申请日：2013-08-10
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中抢占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
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5.发明申请METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) 有权非线性随机逼近寄存器（SAR）模数转换器（ADCS）的方法与系统公开(公告)号：US20140043175A1
公开(公告)日：2014-02-13
申请号：US13964043
申请日：2013-08-10
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
IPC: H03M1/46
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中抢占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
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Patent Agency Ranking
6.发明申请METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE 有权用于异步连续逼近的模拟数字转换器（ADC）架构的方法和系统公开(公告)号：US20160322985A1
公开(公告)日：2016-11-03
申请号：US15151042
申请日：2016-05-10
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
CPC classification number: H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
Abstract: Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions
Abstract translation: 提供了用于在信号处理期间检测元稳定性的系统和方法。 元稳定性检测器可以包括定时控制电路，多个信号调整电路和多个信号状态电路。 定时控制电路可以测量模数转换期间每个转换周期的比较时间。 每个信号调整电路可以向信号调整电路的一个或多个输入信号施加逻辑运算，并提供对应的输出信号。 至少一个处理周期，每个信号状态电路可以将与一个或多个输入信号有关的状态信息存储到信号状态电路; 并基于先前存储的信息提供输出信号。 多个信号状态电路，多个信号调节电路和定时控制电路可以被布置为在模数转换期间产生用于控制模数转换器（ADC）的一个或多个控制信号
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7.发明申请METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE 有权用于异步连续逼近的模拟数字转换器（ADC）架构的方法和系统公开(公告)号：US20160006450A1
公开(公告)日：2016-01-07
申请号：US14812327
申请日：2015-07-29
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
CPC classification number: H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
Abstract: Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.
Abstract translation: 提供了用于控制信号处理输出的方法和系统。 在信号处理电路中，通过多个量化级别搜索与模拟输入匹配的量化级别，以及当在特定时间量内搜索失败时，调整信号处理电路的输出的至少一部分。 调整包括将输出的至少部分设置为预定值。 设置输出或其部分可以包括在正常处理路径的输出和被配置用于处理搜索失败的代码生成路径的输出之间进行选择。 可以产生用于控制信号处理电路的输出的产生的定时信息。 定时信息可以用于在通过多个量化级别的搜索期间测量每周期操作时间。
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8.发明授权Method and system for asynchronous successive approximation analog-to-digital convertor (ADC) architecture 有权用于异步逐次逼近模数转换器（ADC）架构的方法和系统公开(公告)号：US09124291B2
公开(公告)日：2015-09-01
申请号：US13945579
申请日：2013-07-18
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
CPC classification number: H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.
Abstract translation: 用于处理信号的系统可以被配置为在数字转换到模拟信号期间检测包括元稳定性事件的特定错误的发生，并且处理任何检测到的元稳定性事件，例如通过调整相应数字的至少一部分 基于元稳定事件检测的输出。 数字输出的调整可以包括至少设置数字输出的一部分，诸如多个预定数字值或模式之一。 系统可以包括用于生成和/或输出预定数字值或码型的码发生器。 系统可以包括选择器，用于针对数字输出的部分，在正常处理路径的输出之间和预定义的值或模式之间自适应地选择。
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公开(公告)号：US10003347B2
公开(公告)日：2018-06-19
申请号：US15711177
申请日：2017-09-21
Applicant: Maxlinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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公开(公告)号：US20170134032A1
公开(公告)日：2017-05-11
申请号：US15230735
申请日：2016-08-08
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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