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1.发明申请公开(公告)号：US20190044525A1
公开(公告)日：2019-02-07
申请号：US16154167
申请日：2018-10-08
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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2.发明申请METHOD AND SYSTEM FOR TIME INTERLEAVED ANALOG-TO-DIGITAL CONVERTER TIMING MISMATCH ESTIMATION AND COMPENSATION 有权时间间隔模拟数字转换器时序误差估计与补偿的方法与系统公开(公告)号：US20150124915A1
公开(公告)日：2015-05-07
申请号：US14590250
申请日：2015-01-06
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
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3.发明申请公开(公告)号：US20180069562A1
公开(公告)日：2018-03-08
申请号：US15812365
申请日：2017-11-14
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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公开(公告)号：US10097193B2
公开(公告)日：2018-10-09
申请号：US15812365
申请日：2017-11-14
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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公开(公告)号：US20170163277A1
公开(公告)日：2017-06-08
申请号：US15436088
申请日：2017-02-17
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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Patent Agency Ranking
6.发明授权Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权时间交错模数转换器定时失配估计和补偿的方法和系统公开(公告)号：US09577655B2
公开(公告)日：2017-02-21
申请号：US14920699
申请日：2015-10-22
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，使用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
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公开(公告)号：US10326462B2
公开(公告)日：2019-06-18
申请号：US16154167
申请日：2018-10-08
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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公开(公告)号：US09825640B2
公开(公告)日：2017-11-21
申请号：US15436088
申请日：2017-02-17
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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9.发明申请Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation 有权时间交错模数转换器时序不匹配估计和补偿的方法和系统公开(公告)号：US20160043731A1
公开(公告)日：2016-02-11
申请号：US14920699
申请日：2015-10-22
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 以及通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
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10.发明授权Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权时间交错模数转换器定时失配估计和补偿的方法和系统公开(公告)号：US09172386B2
公开(公告)日：2015-10-27
申请号：US14590250
申请日：2015-01-06
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
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