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    Integrated Assemblies and Methods Forming Integrated Assemblies
    2.
    发明申请
    Integrated Assemblies and Methods Forming Integrated Assemblies 有权

    公开(公告)号：US20220344450A1

    公开(公告)日：2022-10-27

    申请号：US17236589

    申请日：2021-04-21

    Applicant: Micron Technology, Inc.

    Inventor： Che-Chi Lee

    IPC: H01L49/02 ,  H01L27/108

    Abstract: Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

    Integrated Assemblies and Methods Forming Integrated Assemblies
    3.
    发明公开
    Integrated Assemblies and Methods Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20230178586A1

    公开(公告)日：2023-06-08

    申请号：US18102661

    申请日：2023-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Che-Chi Lee

    IPC: H10B12/00

    CPC classification number: H01L28/75 ,  H01L28/88 ,  H01L28/92 ,  H10B12/315 ,  H10B12/0335

    Abstract: Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

    Semiconductor structure stack
    4.
    发明授权
    Semiconductor structure stack 有权

    公开(公告)号：US10825691B1

    公开(公告)日：2020-11-03

    申请号：US16555470

    申请日：2019-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Che-Chi Lee

    IPC: H01L21/311 ,  H01L21/02 ,  H01L27/108

    Abstract: Methods, apparatuses, and systems related to stack a semiconductor structure are described. An example method includes stacking a semiconductor structure between electrode materials having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a third silicate material on the second nitride. The method further includes forming a third nitride on the third silicate material. The method further includes using a wet etch process to increase a width between electrode materials. The method further includes using a dry etch process to remove a portion of materials within the semiconductor structure.

    CELL CONTACT
    5.
    发明申请
    CELL CONTACT 审中-公开

    公开(公告)号：US20190148136A1

    公开(公告)日：2019-05-16

    申请号：US15812274

    申请日：2017-11-14

    Applicant: Micron Technology, Inc.

    Inventor： Che-Chi Lee ,  Hiromitsu Oshima

    IPC: H01L21/027 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H01L21/0276 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

    Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.

    Integrated assemblies and methods forming integrated assemblies
    6.
    发明授权
    Integrated assemblies and methods forming integrated assemblies 有权

    公开(公告)号：US11616119B2

    公开(公告)日：2023-03-28

    申请号：US17236589

    申请日：2021-04-21

    Applicant: Micron Technology, Inc.

    Inventor： Che-Chi Lee

    IPC: H01L27/14 ,  H01L21/336 ,  H01L49/02 ,  H01L27/108

    Abstract: Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

    Cell contact
    8.
    发明授权
    Cell contact 有权

    公开(公告)号：US10347487B2

    公开(公告)日：2019-07-09

    申请号：US15812274

    申请日：2017-11-14

    Applicant: Micron Technology, Inc.

    Inventor： Che-Chi Lee ,  Hiromitsu Oshima

    IPC: H01L21/02 ,  H01L21/027 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

    Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.

    MEMORY CELL SUPPORT LATTICE
    9.
    发明申请
    MEMORY CELL SUPPORT LATTICE 审中-公开
    记忆体支持实验室

    公开(公告)号：US20160043089A1

    公开(公告)日：2016-02-11

    申请号：US14877212

    申请日：2015-10-07

    Applicant: Micron Technology, Inc.

    Inventor： Zhimin Song ,  Che-Chi Lee ,  Brett Busch

    IPC: H01L27/108 ,  H01L21/02 ,  H01L21/311

    CPC classification number: H01L27/10852 ,  H01L21/02266 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10814 ,  H01L27/10817 ,  H01L28/91

    Abstract: Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask.

    Abstract translation: 本文描述了记忆单元支撑晶格及其形成方法。 作为示例，形成存储单元支撑晶格的方法包括在阵列中的多个电容器元件上形成掩模，使得垂直和水平相邻的电容器元件之间的空间被完全覆盖，并且对角相邻的电容器元件之间的空间是 部分地覆盖并通过蚀刻支撑材料在支撑材料中形成支撑格架，以将掩模中开口下方的支撑材料的部分去除。

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