公开(公告)号：US20240153542A1

公开(公告)日：2024-05-09

申请号：US17980828

申请日：2022-11-04

Applicant: Micron Technology, Inc

Inventor： Martin Brox ,  Martin Bach ,  Thomas Hein

IPC: G11C7/02 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C7/1039

Abstract: Methods, systems, and devices for voltage overshoot mitigation at a device are described. The device may include a first driver circuit configured to generate data symbols on a transmission line and may include a second driver circuit configured to pre-emphasize the data symbols on the transmission line. The device may include a first inductor and a second inductor in series with the transmission line. A conductive line may couple the second driver circuit with a node, of the transmission line, that is between the first inductor and the second inductor.

公开(公告)号：US20250069631A1

公开(公告)日：2025-02-27

申请号：US18771448

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Martin Bach ,  Miljana Nenadovic ,  Hemant Madhewar ,  Mani Balakrishnan ,  Thomas Hein ,  Martin Brox

IPC: G11C7/22 ,  G11C7/10

Abstract: Methods, systems, and devices for data alignment for memory are described. A memory device may implement individual time adjustments to align portions of a multilevel signal modulated by a modulation scheme with three levels. In some cases, signal paths for generating and transmitting the portions of the multilevel signal may reference a clock signal, and adjustable delay circuits may apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit may apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit may apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Applying the time adjustments to the signal paths may align the portions of the multilevel signal in time, compared to the clock signal.

公开(公告)号：US20250044826A1

公开(公告)日：2025-02-06

申请号：US18763965

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Marcos Alvarez Gonzalez ,  Andrea Sorrentino ,  Morshed Mohammed ,  Luiza Souza Correa ,  Wolfgang Anton Spirkl ,  Paritosh Piyush Sahu ,  Martin Bach ,  Ronny Schneider

IPC: G06F1/10

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. As part of a low-speed testing phase of a memory system, a low-speed tester may measure the change in phase of a set of clock signals in response to a change in a configuration of the memory system. For example, the low-speed tester may communicate with a mimic circuit of the memory system to determine a first frequency of a first clock signal of the multi-phase clock associated with a first configuration of the memory system and determine a second frequency of the first clock signal associated with a second configuration of the memory system. The low-speed tester may store an indication of the difference between the first frequency and the second frequency, and a high-speed tester may use the difference as part of selecting a set of trim parameters for the multi-phase clock signal.

公开(公告)号：US20240304227A1

公开(公告)日：2024-09-12

申请号：US18597576

申请日：2024-03-06

Applicant: Micron Technology, Inc.

Inventor： Martin Bach

IPC: G11C7/10 ,  G11C7/14 ,  H03K19/017

CPC classification number: G11C7/106 ,  G11C7/14 ,  H03K19/01742

Abstract: Methods, systems, and devices for techniques to configure drivers are described. A memory device may calibrate a set of drivers at multiple reference voltages corresponding to different signal values of the drivers. In some examples, a driver associated with transmitting data may include an inductor and the memory device may include a calibration circuit to identify one or more configurations for a set of pull-up circuits and a set of pull-down circuits of the driver both with and without the inductor. The calibration circuit may compare an output of a first pull-up circuit isolated from the inductor with one or more reference voltages, compare an output of a second pull-up circuit coupled with the inductor with the one or more reference voltages, and compare an output of a pull-down circuit isolated from the inductor to the one or more reference voltages.