公开(公告)号：US11651952B2

公开(公告)日：2023-05-16

申请号：US17168393

申请日：2021-02-05

Applicant: Micron Technology, Inc.

Inventor： Michael T. Andreas ,  Jerome A. Imonigie ,  Prashant Raghu ,  Sanjeev Sapra ,  Ian K. McDaniel

IPC: H01L21/02 ,  B81C1/00

CPC classification number: H01L21/02057 ,  B81C1/00849 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02334 ,  B81C2201/0108

Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.

公开(公告)号：US11469103B2

公开(公告)日：2022-10-11

申请号：US17153997

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Sanjeev Sapra ,  Anish A. Khandekar ,  Shen Hu

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8238

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

公开(公告)号：US10777561B2

公开(公告)日：2020-09-15

申请号：US16258987

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sanjeev Sapra ,  Masihhur R. Laskar ,  Darwin Franseda Fan ,  Jerome A. Imonigie

IPC: H01L27/108

Abstract: Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.

公开(公告)号：US20200243536A1

公开(公告)日：2020-07-30

申请号：US16258933

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Diem Thy N. Tran ,  Sanjeev Sapra

IPC: H01L27/108 ,  H01L27/105

Abstract: Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.

公开(公告)号：US09653307B1

公开(公告)日：2017-05-16

申请号：US15210249

申请日：2016-07-14

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Ian C. Laboriante ,  Michael T. Andreas ,  Sanjeev Sapra ,  Prashant Raghu

IPC: H01L21/306 ,  C09D5/16 ,  C09D7/12

CPC classification number: H01L21/306 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/321

Abstract: A surface modification composition comprising a silylation agent comprising a silyl acetamide, a silylation catalyst comprising a perfluoro acid anhydride, an amine-based complexing agent, and an organic solvent. Methods of modifying a silicon-based material and methods of forming high aspect ratio structures on a substrate are also disclosed.

公开(公告)号：US20200381437A1

公开(公告)日：2020-12-03

申请号：US16423684

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Sevim Korkmaz ,  Devesh Dadhich Shreeram ,  Srinivasan Balakrishnan ,  Dewali Ray ,  Sanjeev Sapra ,  Paul A. Paduano

IPC: H01L27/108 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.

公开(公告)号：US10811419B1

公开(公告)日：2020-10-20

申请号：US16419730

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sanket S. Kelkar ,  Gurpreet S. Lugani ,  Paul A. Paduano ,  Matthew N. Rocklein ,  Sanjeev Sapra ,  Christopher W. Petz

IPC: H01L27/108 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to shaping a storage node material are described. An example method includes forming a pillar with a pattern of materials. The method further includes depositing a storage node material on a side of the pillar. The method further includes etching sacrificial materials within the pillar. The method further includes etching the storage node material in a direction from the pillar into the storage node.

公开(公告)号：US20200243528A1

公开(公告)日：2020-07-30

申请号：US16258987

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sanjeev Sapra ,  Masihhur R. Laskar ,  Darwin Franseda Fan ,  Jerome A. Imonigie

IPC: H01L27/108

Abstract: Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient B SPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.

公开(公告)号：US10546923B2

公开(公告)日：2020-01-28

申请号：US16446780

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Pranav P. Sharma ,  Vinay Nair ,  Sanjeev Sapra

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L27/108 ,  H01L23/64

Abstract: Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat-topped peak portion and an adjacent concavity portion.

公开(公告)号：US20190312103A1

公开(公告)日：2019-10-10

申请号：US16446780

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Pranav P. Sharma ,  Vinay Nair ,  Sanjeev Sapra

IPC: H01L29/06 ,  H01L29/161 ,  H01L23/64 ,  H01L27/108 ,  H01L29/20

Abstract: Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat-topped peak portion and an adjacent concavity portion.