公开(公告)号：US20030178474A1

公开(公告)日：2003-09-25

申请号：US10106009

申请日：2002-03-25

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang ,  Tsuyoshi Yamashita

IPC: B23K001/20

CPC classification number: H01L21/563 ,  B23K2101/40 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method for assembling chips onto substrates includes applying a flux-free, no-flow underfill material. In an embodiment, the method includes removing oxide from interconnects without the use of a flux and applying a flux-free, no-flow underfill. In an embodiment, the method includes removing oxide from bumps, applying no-flow underfill to a substrate, and fluxlessly connecting the bumps to pads on the substrate. In an embodiment, oxide is removed from the bumps by a plasma treatment. In an embodiment, oxide is removed from the bumps by a subjecting the bumps to an oxide reduction process. The assembly of the chips and substrate is free from flux residue and/or flux cleaning solution residue.

Abstract translation: 将芯片组装到衬底上的方法包括施加无助焊剂的无流动的底部填充材料。 在一个实施例中，该方法包括从互连中去除氧化物而不使用焊剂并施加无助熔剂的无流动底部填充物。 在一个实施例中，该方法包括从凸起去除氧化物，向衬底施加无流动的底部填充物，以及将所述凸起与所述衬底上的焊盘无磁通地连接。 在一个实施例中，通过等离子体处理从凸块去除氧化物。 在一个实施例中，通过使凸块进行氧化物还原处理，从凸块去除氧化物。 芯片和基板的组装没有助焊剂残渣和/或助焊剂清洗溶液残留物。

公开(公告)号：US20020020908A1

公开(公告)日：2002-02-21

申请号：US09971952

申请日：2001-10-04

Applicant: Micron Technology, Inc.

Inventor： Casey Prindiville ,  Tongbi Jiang ,  Bret Street

IPC: H01L023/22

CPC classification number: H01L22/20 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/4913 ,  H01L2224/85 ,  H01L2924/00

Abstract: Semiconductor package support elements including cover members attached to one or more reject die sites are provided. Methods for making the support elements of the present invention and for making semiconductor packages using the same are also provided. Reject die sites on defective substrates of a support element are covered prior to the encapsulation process using a cover member. The cover member comprises, for example, pressure sensitive or temperature-activated tape, reject dies, or the like. The support elements and methods of the present invention virtually eliminate bleeding or flashing during encapsulation due to the presence of reject die sites. The support elements and methods of the present invention further ensure that functional dice are not sacrificed by being attached to reject die sites, thereby decreasing manufacturing costs while increasing yield of functional semiconductor packages.

Abstract translation: 提供了包括附接到一个或多个废弃模具位置的盖构件的半导体封装支撑元件。 还提供了制造本发明的支撑元件和制造使用其的半导体封装件的方法。 在使用盖构件的封装工艺之前，覆盖支撑元件的有缺陷的基底上的模具位置。 盖构件例如包括压敏或温度驱动带，废模等。 本发明的支撑元件和方法由于存在废弃模具位置而实际上消除了在封装期间的渗出或闪烁。 本发明的支撑元件和方法进一步确保功能性骰子不会被附着到废弃模具位置而牺牲，从而降低制造成本，同时提高功能性半导体封装的产量。

公开(公告)号：US20040217463A1

公开(公告)日：2004-11-04

申请号：US10857738

申请日：2004-05-28

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang ,  Yong Du

IPC: H01L023/14

CPC classification number: H01L23/145 ,  H01L23/13 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/036 ,  H05K1/0366 ,  H05K2201/0191 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00012

Abstract: This invention relates to circuit boards and methods of fabricating circuit boards. A circuit board includes a core layer and a surface layer. The core layer includes a number of fibers and the surface layer has a thickness that is between about 10% and about 30% of the circuit board thickness. Including fibers in the core layer increases the strength of the circuit board. The surface layer is essentially free of fibers and relatively thick. The thickness of the surface layer inhibits the formation of cracks in the circuit board, which improves the reliability of circuits and systems coupled to the circuit board.

Abstract translation: 本发明涉及电路板及制造电路板的方法。 电路板包括芯层和表面层。 芯层包括许多纤维，表面层的厚度在电路板厚度的约10％至约30％之间。 在芯层中包括纤维增加了电路板的强度。 表面层基本上不含纤维并且较厚。 表面层的厚度抑制电路板中的裂缝的形成，这提高了与电路板耦合的电路和系统的可靠性。

公开(公告)号：US20040089171A1

公开(公告)日：2004-05-13

申请号：US10701140

申请日：2003-11-04

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang ,  Chad A. Cobbley ,  John VanNortwick

IPC: B41C001/14

CPC classification number: B41C1/14 ,  B41N1/242 ,  H01L2224/4826 ,  H05K3/1225 ,  Y10S438/945

Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

Abstract translation: 公开了一种用于改进模板/丝网印刷质量的方法和装置。 在片上（LOC）包装过程中，模板或屏幕有助于将可印刷材料施加到基底上，例如对半导体晶片的半导体管芯的粘合剂。 在一个实施例中，模板包括施加到模板或筛网的图案的至少一个表面上的涂层，以阻止可印刷材料运动到表面上。 在另一个实施例中，模板或丝网包括施加到图案的至少一个其他表面的第二涂层，以促进可印刷材料在基底上的铺展。

公开(公告)号：US20030067083A1

公开(公告)日：2003-04-10

申请号：US10230005

申请日：2002-08-28

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang ,  Michael E. Connell

IPC: H01L023/12

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto. In another aspect, the present invention is directed to a plurality of stacked semiconductor devices that comprise a first die, the first die having an upper surface, a second die positioned above the first die, the second die having a bottom surface, and an adhesive layer positioned between and coupled to each of the first die and the second die, the adhesive layer comprised of first and second surfaces, the first surface of the adhesive layer being coupled to the bottom surface of the second die thereby defining a first contact area, the second surface of the adhesive layer being coupled to the upper surface of the first die thereby defining a second contact area, the second contact area being less than the first contact area.

公开(公告)号：US20020020902A1

公开(公告)日：2002-02-21

申请号：US09971985

申请日：2001-10-04

Applicant: Micron Technology, Inc.

Inventor： Casey Prindiville ,  Tongbi Jiang ,  Bret Street

IPC: H01L023/02

CPC classification number: H01L22/20 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/4913 ,  H01L2224/85 ,  H01L2924/00

Abstract: Semiconductor package support elements including cover members attached to one or more reject die sites are provided. Methods for making the support elements of the present invention and for making semiconductor packages using the same are also provided. Reject die sites on defective substrates of a support element are covered prior to the encapsulation process using a cover member. The cover member comprises, for example, pressure-sensitive or temperature-activated tape, reject dies, or the like. The support elements and methods of the present invention virtually eliminate bleeding or flashing during encapsulation due to the presence of reject die sites. The support elements and methods of the present invention further ensure that functional dice are not sacrificed by being attached to reject die sites, thereby decreasing manufacturing costs while increasing yield of functional semiconductor packages.

公开(公告)号：US20010052267A1

公开(公告)日：2001-12-20

申请号：US09922966

申请日：2001-08-06

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang ,  Zhigiang Wu

IPC: G01L001/16

CPC classification number: G01L1/205

Abstract: A high-resolution pressure-sensing device is disclosed. The device includes an insulating flexible matrix having a plurality of filler particles. Application of a force to the matrix causes compression of the matrix. This results in the filler particles occupying a greater amount of space within the matrix relative to when no force is applied. A detector attached to the matrix detects or measures the volume of the filler particles relative to the volume of the matrix, and therefore determines the force applied to the matrix. Preferably, the resistivity of the matrix is inversely proportional to the volume percent of the filler particles, in which case the detector is a resistance-measuring circuit.

Abstract translation: 公开了一种高分辨率压力感测装置。 该装置包括具有多个填料颗粒的绝缘柔性基质。 对矩阵施加力会导致矩阵的压缩。 这导致在没有施加力的情况下，填料颗粒在基质内占据更大量的空间。 连接到基体的检测器检测或测量填料颗粒相对于基体体积的体积，因此确定施加到基质上的力。 优选地，基质的电阻率与填料颗粒的体积百分比成反比，在这种情况下，检测器是电阻测量电路。

公开(公告)号：US20040107902A1

公开(公告)日：2004-06-10

申请号：US10643567

申请日：2003-08-19

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang ,  Chad A. Cobbley ,  John VanNortwick

IPC: B05C005/00 ,  B05C011/11

CPC classification number: B41C1/14 ,  B41N1/242 ,  H01L2224/4826 ,  H05K3/1225 ,  Y10S438/945

Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

Abstract translation: 公开了一种用于改进模板/丝网印刷质量的方法和装置。 在片上（LOC）包装过程中，模板或屏幕有助于将可印刷材料施加到基底上，例如对半导体晶片的半导体管芯的粘合剂。 在一个实施例中，模板包括施加到模板或筛网的图案的至少一个表面上的涂层，以阻止可印刷材料在表面上的运行。 在另一个实施例中，模板或丝网包括施加到图案的至少一个其他表面的第二涂层，以促进可印刷材料在基底上的铺展。

公开(公告)号：US20020096554A1

公开(公告)日：2002-07-25

申请号：US10020107

申请日：2001-12-07

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang ,  Zhiqiang Wu

IPC: B23K001/06 ,  B23K005/20 ,  B23K020/10 ,  B23K031/02

CPC classification number: H01L24/85 ,  B23K20/004 ,  B23K2101/38 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/78301 ,  H01L2224/78347 ,  H01L2224/78822 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85206 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/20303 ,  H01L2924/20305 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015

Abstract: A method and apparatus for creating second order vibrational modes. The apparatus includes a signal generator, a piezoelectric transducer, a plurality of wave propagating beams and reflecting boards. An electric field applied by the signal generator to the piezoelectric transducer induces a unidirectional vibration of the transducer. The vibration is propagated through the beams and reflected by the reflecting boards in a closed polygonal loop. The final reflection direction is perpendicular to the original vibration. A circular or elliptical vibration of the apparatus results. The circular or elliptical vibrational energy can be imparted to the wire bond of an integrated circuit to add strength to the connection.

Abstract translation: 一种用于创建二阶振动模式的方法和装置。 该装置包括信号发生器，压电换能器，多个波传播光束和反射板。 由信号发生器施加到压电换能器的电场引起换能器的单向振动。 振动通过光束传播并被反射板以闭合的多边形回路反射。 最终反射方向与原始振动垂直。 该装置产生圆形或椭圆形的振动。 可以将圆形或椭圆形振动能量赋予集成电路的引线键合，以增加连接的强度。

公开(公告)号：US20040157361A1

公开(公告)日：2004-08-12

申请号：US10365998

申请日：2003-02-12

Applicant: Micron Technology, Inc.

Inventor： Tongbi Jiang

IPC: H01L021/44

CPC classification number: H01L23/544 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies.

Abstract translation: 本发明提供了制造积层单芯片或多芯片模块的技术。 在一个实施例中，这通过在衬底上的一个或多个预蚀刻空腔中分配管芯附着材料来实现。 然后通过在衬底上施加略微向下的压力将半导体管芯放置在包括管芯附接材料的每个预蚀刻腔体上，使得每个放置的半导体管芯的有源表面跨过衬底设置，并且进一步基本上与 基质。 然后通过固化管芯附着材料将半导体管芯固定到衬底上。 然后，在衬底和每个半导体管芯的有源表面上形成包括一个或多个交替层的电介质材料和金属化结构的微型电路板，以使半导体管芯互连。