High resolution pressure-sensing device having an insulating flexible matrix loaded with filler particles

    公开(公告)号:US20030115970A1

    公开(公告)日:2003-06-26

    申请号:US10366822

    申请日:2003-02-14

    CPC classification number: G01L1/205

    Abstract: A high-resolution pressure-sensing device is disclosed. The device includes an insulating flexible matrix having a plurality of filler particles. Application of a force to the matrix causes compression of the matrix. This results in the filler particles occupying a greater amount of space within the matrix relative to when no force is applied. A detector attached to the matrix detects or measures the volume of the filler particles relative to the volume of the matrix, and therefore determines the force applied to the matrix. Preferably, the resistivity of the matrix is inversely proportional to the volume percent of the filler particles, in which case the detector is a resistance-measuring circuit.

    Method and apparatus for reducing isolation stress in integrated circuits
    2.
    发明申请
    Method and apparatus for reducing isolation stress in integrated circuits 失效
    降低集成电路隔离应力的方法和装置

    公开(公告)号:US20020163056A1

    公开(公告)日:2002-11-07

    申请号:US10188472

    申请日:2002-07-02

    CPC classification number: H01L21/32 H01L21/0332

    Abstract: Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially linear or non-linear fashion. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, stress is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.

    Abstract translation: 通过用具有梯度硅浓度的氮化硅形成氧化掩模来减小机械应力。 通过改变氮化硅中的硅含量来实现分级。 氮化硅可以以基本线性或非线性方式分级。 在一个实施例中,渐变氮化硅可以用一种类型的非线性硅分级,突变结形成。 在其它实施例中,氮化硅形成为在氮化硅生长期间或之后形成的各种形状。 在一个实施例中,通过在两个氮化硅层之间形成多晶硅缓冲层来减小应力。 在另一个实施例中,通过在衬底层上形成氮化硅来降低应力,衬底层又形成在基底层上。

    Novel zero insertion force sockets using negative thermal expansion materials
    3.
    发明申请
    Novel zero insertion force sockets using negative thermal expansion materials 审中-公开
    使用负热膨胀材料的新型零插入插座

    公开(公告)号:US20010001084A1

    公开(公告)日:2001-05-10

    申请号:US09740751

    申请日:2000-12-19

    Abstract: A socket device for receiving a connection pin is disclosed, the socket device including a substrate having an upper surface. The socket device includes a connection pad disposed on the upper surface and a first layer disposed on the upper surface and on the connection pad. The first layer includes material having an overall positive coefficient of thermal expansion. The socket device includes a second layer disposed on the first layer. The second layer includes material having an overall negative coefficient of thermal expansion. The socket device also includes a contact hole formed in the first and second layers exposing a portion of the connection pad.

    Abstract translation: 公开了一种用于接收连接销的插座装置,插座装置包括具有上表面的基板。 插座装置包括设置在上表面上的连接垫和设置在上表面上和连接垫上的第一层。 第一层包括具有总体正的热膨胀系数的材料。 插座装置包括设置在第一层上的第二层。 第二层包括具有总体负的热膨胀系数的材料。 插座装置还包括形成在第一和第二层中的接触孔,露出连接垫的一部分。

    Capacitor structure
    4.
    发明申请

    公开(公告)号:US20020140020A1

    公开(公告)日:2002-10-03

    申请号:US10145435

    申请日:2002-05-14

    CPC classification number: H01L27/10852 H01L28/82

    Abstract: The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

    Capacitor structure
    5.
    发明申请
    Capacitor structure 有权
    电容结构

    公开(公告)号:US20020135011A1

    公开(公告)日:2002-09-26

    申请号:US10145250

    申请日:2002-05-14

    CPC classification number: H01L27/10852 H01L28/82

    Abstract: The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

    Abstract translation: 本发明涉及一种电容器的制造,该电容器形成为具有大致凹入形状且具有可选择的折叠或回旋表面。 凹形形状在小体积内优化表面积,从而使电容器能够保持大量电荷,从而有助于微电子领域中的增加的小型化努力。 电容器以与电致密DRAM阵列一致的微电子方式制造。 制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

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