公开(公告)号：US09287221B2

公开(公告)日：2016-03-15

申请号：US14591010

申请日：2015-01-07

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/311 ,  H01L21/762 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

Abstract translation: 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US08828842B2

公开(公告)日：2014-09-09

申请号：US14172919

申请日：2014-02-05

Applicant: Nanya Technology Corp.

Inventor： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/762 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L21/76224 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

公开(公告)号：US20150194390A1

公开(公告)日：2015-07-09

申请号：US14591010

申请日：2015-01-07

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

Abstract translation: 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US08865550B2

公开(公告)日：2014-10-21

申请号：US14184725

申请日：2014-02-20

Applicant: Nanya Technology Corp.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/66 ,  H01L29/66 ,  H01L27/108 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

公开(公告)号：US20140213027A1

公开(公告)日：2014-07-31

申请号：US14184725

申请日：2014-02-20

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

Abstract translation: 提供一种形成掩埋位线的方法。 提供衬底并且在衬底中限定线状沟槽区域。 在基板的线状沟槽区域中形成线状沟槽。 线状沟槽包括侧壁表面和底部表面。 然后，将线状沟槽的底面加宽，形成弯曲的底面。 接下来，在与该弯曲底面相邻的基板上形成掺杂区域。 最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

公开(公告)号：US20140154864A1

公开(公告)日：2014-06-05

申请号：US14172919

申请日：2014-02-05

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

Abstract translation: 本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US20130307067A1

公开(公告)日：2013-11-21

申请号：US13958620

申请日：2013-08-05

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/423

CPC classification number: H01L29/4236 ,  H01L21/28114 ,  H01L21/76224 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66553

Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.

Abstract translation: 提供狭缝凹槽通道门。 狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。 衬底具有第一沟槽。 栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。 第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。

公开(公告)号：US09093471B2

公开(公告)日：2015-07-28

申请号：US14534192

申请日：2014-11-06

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

Abstract: A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate.

Abstract translation: 一种形成沟槽MOS结构的方法。 首先，提供衬底，外延层，掺杂区和掺杂阱。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 栅极沟槽穿透掺杂区域和掺杂阱。 部分去除掺杂阱以形成栅极沟槽的底部。 形成栅极隔离以覆盖底部的内壁和栅极沟槽的顶部。 栅极沟槽填充有导电材料以形成沟槽栅极。

公开(公告)号：US20150064893A1

公开(公告)日：2015-03-05

申请号：US14534192

申请日：2014-11-06

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

Abstract: A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate.

Abstract translation: 一种形成沟槽MOS结构的方法。 首先，提供衬底，外延层，掺杂区和掺杂阱。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 栅极沟槽穿透掺杂区域和掺杂阱。 部分去除掺杂阱以形成栅极沟槽的底部。 形成栅极隔离以覆盖底部的内壁和栅极沟槽的顶部。 栅极沟槽填充有导电材料以形成沟槽栅极。

公开(公告)号：US08698235B2

公开(公告)日：2014-04-15

申请号：US13958620

申请日：2013-08-05

Applicant: Nanya Technology Corp.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4236 ,  H01L21/28114 ,  H01L21/76224 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66553

Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.

Abstract translation: 提供狭缝凹槽通道门。 狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。 衬底具有第一沟槽。 栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。 第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。