公开(公告)号：US11169779B2

公开(公告)日：2021-11-09

申请号：US16803795

申请日：2020-02-27

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang

IPC: G06F7/501 ,  G06F9/30 ,  G06F7/575 ,  G06F7/509 ,  G06F7/533 ,  H03K19/21 ,  G06F7/53

Abstract: An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

公开(公告)号：US20210124558A1

公开(公告)日：2021-04-29

申请号：US16803795

申请日：2020-02-27

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang

IPC: G06F7/501 ,  G06F7/575 ,  G06F9/30

Abstract: An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

公开(公告)号：US20210124559A1

公开(公告)日：2021-04-29

申请号：US16661888

申请日：2019-10-23

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang

IPC: G06F7/509 ,  G06F7/533 ,  G06F7/53

Abstract: This disclosure relates to an adder circuit. The adder circuit comprises an operand input and a second operand input to an XNOR cell. The XNOR cell may be configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell may transform the output of the XNOR cell into a carry out signal.

公开(公告)号：US10466968B1

公开(公告)日：2019-11-05

申请号：US16033468

申请日：2018-07-12

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin

IPC: G06F7/523 ,  G06F7/49

Abstract: A system including a series of partial product select encoders and partial product muxes, each of the partial product select encoders receiving a multiplier, receiving a carry input from a multiplier tree, and outputting a select signal to an associated partial product mux based on the multiplier and carry input, and each of the partial product muxes outputting a partial product based on the select signal and a multiplicand received.

公开(公告)号：US20240160406A1

公开(公告)日：2024-05-16

申请号：US18484790

申请日：2023-10-11

Applicant: NVIDIA Corp.

Inventor： Rangharajan Venkatesan ,  Reena Elangovan ,  Charbel Sakr ,  Brucek Kurdo Khailany ,  Ming Y Siu ,  Ilyas Elkin ,  Brent Ralph Boswell

IPC: G06F7/487 ,  G06F7/499

CPC classification number: G06F7/4876 ,  G06F7/49915

Abstract: Mechanisms to exploit the inherent resiliency of deep learning inference workloads to improve the energy efficiency of computer processors such as graphics processing units with these workloads. The mechanisms provide energy-accuracy tradeoffs in the computation of deep learning inference calculations via energy-efficient floating point data path micro-architectures with integer accumulation, and enhanced mechanisms for per-vector scaled quantization (VS-Quant) of floating-point arguments.

公开(公告)号：US11294631B2

公开(公告)日：2022-04-05

申请号：US16661888

申请日：2019-10-23

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang

IPC: G06F7/509 ,  G06F7/53 ,  G06F7/533 ,  H03K19/21 ,  G06F7/501 ,  G06F9/30 ,  G06F7/575

Abstract: An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.