公开(公告)号：US20240395293A1

公开(公告)日：2024-11-28

申请号：US18323997

申请日：2023-05-25

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Jason Golbus ,  Jesse San-Jey Wang

IPC: G11C7/10 ,  G11C7/18

Abstract: Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets.

公开(公告)号：US20240420748A1

公开(公告)日：2024-12-19

申请号：US18336758

申请日：2023-06-16

Applicant: NVIDIA Corp.

Inventor： Cagri Erbagci ,  Burak Erbagci ,  Lalit Gupta ,  Jesse San-Jey Wang

IPC: G11C7/12 ,  G11C7/10

Abstract: Negative bit line voltage assist mechanisms for multi-bank machine memories utilizing multiple local IO drivers include a shared boost capacitor configured to generate a negative bit line voltage assist for write operations by local IO drivers, where the boost capacitor is configured to selectively couple to one of the local IO drivers during the write operation.

公开(公告)号：US20240161815A1

公开(公告)日：2024-05-16

申请号：US18055047

申请日：2022-11-14

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Jason Golbus ,  Jesse San-Jey Wang

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4094

Abstract: Multi-ported memories that include write peripheral logic configured to operate in a first voltage domain, read peripheral logic configured to operate in a second voltage domain, and at least one bit cell array, wherein the write peripheral logic and the read peripheral logic are disposed on opposite sides of the bit cell array and voltage domain crossings between the first voltage domain and the second voltage domain are localized in bit cells of the at least one bit cell array.