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公开(公告)号：US12248699B2
公开(公告)日：2025-03-11
申请号：US18332766
申请日：2023-06-12
Applicant: PHISON ELECTRONICS CORP.
Inventor： Cheng-Jui Chou , Kuen-Chih Lin
Abstract: A clock control circuit, a memory storage device, and a clock control method are disclosed. The method includes: tracking a frequency of a first signal from a host system; generating, in a first mode, a clock signal according to the frequency of the first signal; and generating, in a second mode, the clock signal without reference to the frequency of the first signal.
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2.发明申请公开(公告)号：US20180210652A1
公开(公告)日：2018-07-26
申请号：US15456584
申请日：2017-03-13
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Ming Chen , An-Chung Chen , Kuen-Chih Lin
IPC: G06F3/06
Abstract: An exemplary embodiment of the present disclosure provides a reference clock signal generation method for a memory storage device. The method includes: receiving a first type signal from a host system; generating a first control parameter according to a frequency of the first type signal; receiving a second type signal from the host system after the first type signal is received; generating a second control parameter according to a frequency of the second type signal; and generating a reference clock signal meeting a first condition according to the second control parameter. Therefore, an efficiency of generating the reference clock signal can be improved.
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公开(公告)号：US20240402936A1
公开(公告)日：2024-12-05
申请号：US18332766
申请日：2023-06-12
Applicant: PHISON ELECTRONICS CORP.
Inventor： Cheng-Jui Chou , Kuen-Chih Lin
Abstract: A clock control circuit, a memory storage device, and a clock control method are disclosed. The method includes: tracking a frequency of a first signal from a host system; generating, in a first mode, a clock signal according to the frequency of the first signal; and generating, in a second mode, the clock signal without reference to the frequency of the first signal.
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