公开(公告)号：US11966714B2

公开(公告)日：2024-04-23

申请号：US17588311

申请日：2022-01-30

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

IPC: G11C11/412 ,  G06F7/523 ,  G06F17/16 ,  G06N3/063 ,  G11C11/418 ,  G11C11/419 ,  G11C15/04

CPC classification number: G06F7/523 ,  G06F17/16 ,  G06N3/063 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C15/04

Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.

公开(公告)号：US20220206751A1

公开(公告)日：2022-06-30

申请号：US17588311

申请日：2022-01-30

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

IPC: G06F7/523 ,  G11C11/412 ,  G06N3/063 ,  G11C11/418 ,  G06F17/16 ,  G11C11/419

Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic is disclosed which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.

公开(公告)号：US11281429B2

公开(公告)日：2022-03-22

申请号：US16581965

申请日：2019-09-25

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

IPC: G11C11/412 ,  G06F7/523 ,  G06N3/063 ,  G11C11/418 ,  G06F17/16 ,  G11C11/419 ,  G11C15/04

Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.

公开(公告)号：US11688445B2

公开(公告)日：2023-06-27

申请号：US17588317

申请日：2022-01-30

Applicant: Purdue Research Foundation

Inventor： Sandeep Krishna Thirumala ,  Sumeet Kumar Gupta ,  Yi-Tse Hung ,  Zhihong Chen

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/18 ,  H10B61/00 ,  H10N52/80 ,  H10N52/00

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H10B61/00 ,  H10N52/101 ,  H10N52/80

Abstract: A memory cell is disclosed which includes a semiconductor layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another along a first axis and wherein the semiconductor layer extends beyond the first axis along a second axis substantially perpendicular to the first axis, thereby forming a first wing, a third electrode separated from the semiconductor layer by an insulating layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.

公开(公告)号：US20220157359A1

公开(公告)日：2022-05-19

申请号：US17588317

申请日：2022-01-30

Applicant: Purdue Research Foundation

Inventor： Sandeep Krishna Thirumala ,  Sumeet Kumar Gupta ,  Yi-Tse Hung ,  Zhihong Chen

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  G11C11/18 ,  H01L43/06

Abstract: A memory cell is disclosed which includes a semiconductor layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another along a first axis and wherein the semiconductor layer extends beyond the first axis along a second axis substantially perpendicular to the first axis, thereby forming a first wing, a third electrode separated from the semiconductor layer by an insulating layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.

公开(公告)号：US11296224B1

公开(公告)日：2022-04-05

申请号：US17349898

申请日：2021-06-16

Applicant: Purdue Research Foundation

Inventor： Niharika Thakuria ,  Sumeet Kumar Gupta

IPC: G11C11/22 ,  H01L29/78 ,  H01L29/76 ,  H01L27/1159 ,  H01L29/24 ,  H01L29/51

Abstract: A polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cell is disclosed which includes a transistor including a source contact, a drain contact, a gate contact, a back contact, a channel disposed atop the gate contact, wherein the channel and the gate are separated by an electrically insulating material, and a piezoelectric (PE)/ferroelectric(FE) (PE/FE) layer disposed between the gate contact and the back contact and configured to store bit information in form of ferroelectric polarization (P), wherein a ratio of cross-sectional area of the channel to cross-sectional area of the PE/FE layer is between about 0.03 to about 0.07.

公开(公告)号：US11250896B2

公开(公告)日：2022-02-15

申请号：US16909971

申请日：2020-06-23

Applicant: Purdue Research Foundation

Inventor： Sandeep Krishna Thirumala ,  Sumeet Kumar Gupta ,  Yi-Tse Hung ,  Zhihong Chen

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  G11C11/18 ,  H01L43/06

Abstract: A memory cell is disclosed which includes a conductive layer, an insulating layer disposed atop the conducting layer, a semiconductor layer disposed atop the insulating layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another and wherein the semiconductor layer extends beyond the first and second electrodes forming a first wing, a third electrode coupled to the conductive layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.

公开(公告)号：US20210089272A1

公开(公告)日：2021-03-25

申请号：US16581965

申请日：2019-09-25

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

IPC: G06F7/523 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418 ,  G06F17/16 ,  G06N3/063

Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.