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    Approximate cache memory
    1.
    发明授权
    Approximate cache memory 有权

    公开(公告)号：US11151040B2

    公开(公告)日：2021-10-19

    申请号：US16362672

    申请日：2019-03-24

    Applicant: Purdue Research Foundation

    Inventor： Ashish Ranjan ,  Swagath Venkataramani ,  Zoha Pajouhi ,  Rangharajan Venkatesan ,  Kaushik Roy ,  Anand Raghunathan

    IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/0891 ,  G11C11/16 ,  G06F12/0864 ,  G06F12/02

    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

    TOMOGRAPHIC RECONSTRUCTION SYSTEM
    3.
    发明申请
    TOMOGRAPHIC RECONSTRUCTION SYSTEM 有权

    公开(公告)号：US20210110581A1

    公开(公告)日：2021-04-15

    申请号：US17033065

    申请日：2020-09-25

    Applicant: Purdue Research Foundation

    Inventor： Junshi Liu ,  Swagath Venkataramani ,  Singanallur V. Venkatakrishnan ,  Charles A. Bouman ,  Anand Raghunathan

    IPC: G06T11/00

    Abstract: A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.

    TERNARY IN-MEMORY ACCELERATOR
    4.
    发明申请
    TERNARY IN-MEMORY ACCELERATOR 有权

    公开(公告)号：US20210089272A1

    公开(公告)日：2021-03-25

    申请号：US16581965

    申请日：2019-09-25

    Applicant: Purdue Research Foundation

    Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

    IPC: G06F7/523 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418 ,  G06F17/16 ,  G06N3/063

    Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.

    APPROXIMATE CACHE MEMORY
    5.
    发明申请
    APPROXIMATE CACHE MEMORY 审中-公开

    公开(公告)号：US20180365154A1

    公开(公告)日：2018-12-20

    申请号：US15623343

    申请日：2017-06-14

    Applicant: Purdue Research Foundation

    Inventor： Ashish Ranjan ,  Swagath Venkataramani ,  Zoha Pajouhi ,  Rangharajan Venkatesan ,  Kaushik Roy ,  Anand Raghunathan

    IPC: G06F12/0846 ,  G06F12/0891

    CPC classification number: G06F12/0848 ,  G06F12/0846 ,  G06F12/0891 ,  G06F2212/621

    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

    Tomographic reconstruction system
    9.
    发明授权
    Tomographic reconstruction system 有权

    公开(公告)号：US10163232B2

    公开(公告)日：2018-12-25

    申请号：US15063054

    申请日：2016-03-07

    Applicant: Purdue Research Foundation

    Inventor： Junshi Liu ,  Swagath Venkataramani ,  Singanallur V. Venkatakrishnan ,  Charles A. Bouman ,  Anand Raghunathan

    IPC: G06K9/00 ,  G06T11/00

    Abstract: A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.

    System and method for in-memory computing
    10.
    发明授权
    System and method for in-memory computing 有权

    公开(公告)号：US10073733B1

    公开(公告)日：2018-09-11

    申请号：US15693661

    申请日：2017-09-01

    Applicant: Purdue Research Foundation

    Inventor： Shubham Jain ,  Ashish Ranjan ,  Kaushik Roy ,  Anand Raghunathan

    IPC: G11C11/00 ,  G06F11/10

    CPC classification number: G06F11/1016 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/108

    Abstract: A memory capable of carrying out compute-in-memory (CiM) operations is disclosed. The memory includes a matrix of bit cells having a plurality of bit cells along one or more rows and a plurality of bit cells along one or more columns, each bit cell having a value stored therein, an address decoder configured to receive addresses and activate two or more of the rows associated with the addresses, and a sensing circuit coupled to each column of bit cells, and configured to provide two or more outputs, wherein each output is associated with at least one compute operation performed on values stored in the bit cells in the column.

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