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    Tomographic reconstruction system
    3.
    发明授权
    Tomographic reconstruction system 有权

    公开(公告)号：US10163232B2

    公开(公告)日：2018-12-25

    申请号：US15063054

    申请日：2016-03-07

    Applicant: Purdue Research Foundation

    Inventor： Junshi Liu ,  Swagath Venkataramani ,  Singanallur V. Venkatakrishnan ,  Charles A. Bouman ,  Anand Raghunathan

    IPC: G06K9/00 ,  G06T11/00

    Abstract: A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.

    TOMOGRAPHIC RECONSTRUCTION SYSTEM
    4.
    发明申请
    TOMOGRAPHIC RECONSTRUCTION SYSTEM 审中-公开
    全景重建系统

    公开(公告)号：US20160260230A1

    公开(公告)日：2016-09-08

    申请号：US15063054

    申请日：2016-03-07

    Applicant: Purdue Research Foundation

    Inventor： Junshi Liu ,  Swagath Venkataramani ,  Singanallur V. Venkatakrishnan ,  Charles A. Bouman ,  Anand Raghunathan

    IPC: G06T11/00

    CPC classification number: G06T11/006 ,  G06T2211/424 ,  G06T2211/432

    Abstract: A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.

    Abstract translation: 具有中央处理单元，通信地连接到中央处理单元的系统存储器和通信地连接到中央处理单元和系统存储器的硬件​​加速单元的断层摄影系统，所述硬件加速器被配置为执行MBIR的至少一部分 计算机断层扫描数据处理。 硬件加速器单元可以包括一个或多个体素评估模块，其评估在重构体积中给定体素位置的体素的更新值。 通过处理体素邻域中的体素的体素数据，处理时间减少。

    Approximate cache memory
    5.
    发明授权
    Approximate cache memory 有权

    公开(公告)号：US11151040B2

    公开(公告)日：2021-10-19

    申请号：US16362672

    申请日：2019-03-24

    Applicant: Purdue Research Foundation

    Inventor： Ashish Ranjan ,  Swagath Venkataramani ,  Zoha Pajouhi ,  Rangharajan Venkatesan ,  Kaushik Roy ,  Anand Raghunathan

    IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/0891 ,  G11C11/16 ,  G06F12/0864 ,  G06F12/02

    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

    Approximate cache memory
    6.
    发明授权
    Approximate cache memory 有权

    公开(公告)号：US10255186B2

    公开(公告)日：2019-04-09

    申请号：US15623343

    申请日：2017-06-14

    Applicant: Purdue Research Foundation

    Inventor： Ashish Ranjan ,  Swagath Venkataramani ,  Zoha Pajouhi ,  Rangharajan Venkatesan ,  Kaushik Roy ,  Anand Raghunathan

    IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/0891

    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

    TOMOGRAPHIC RECONSTRUCTION SYSTEM
    7.
    发明申请
    TOMOGRAPHIC RECONSTRUCTION SYSTEM 有权

    公开(公告)号：US20210110581A1

    公开(公告)日：2021-04-15

    申请号：US17033065

    申请日：2020-09-25

    Applicant: Purdue Research Foundation

    Inventor： Junshi Liu ,  Swagath Venkataramani ,  Singanallur V. Venkatakrishnan ,  Charles A. Bouman ,  Anand Raghunathan

    IPC: G06T11/00

    Abstract: A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.

    APPROXIMATE CACHE MEMORY
    8.
    发明申请
    APPROXIMATE CACHE MEMORY 审中-公开

    公开(公告)号：US20180365154A1

    公开(公告)日：2018-12-20

    申请号：US15623343

    申请日：2017-06-14

    Applicant: Purdue Research Foundation

    Inventor： Ashish Ranjan ,  Swagath Venkataramani ,  Zoha Pajouhi ,  Rangharajan Venkatesan ,  Kaushik Roy ,  Anand Raghunathan

    IPC: G06F12/0846 ,  G06F12/0891

    CPC classification number: G06F12/0848 ,  G06F12/0846 ,  G06F12/0891 ,  G06F2212/621

    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

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