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公开(公告)号：US11050962B2
公开(公告)日：2021-06-29
申请号：US16040777
申请日：2018-07-20
Applicant: Raytheon Company
Inventor： Jehyuk Rhee
IPC: H04N5/3745 , H04N5/33 , H04N5/378 , H04N5/355 , H01L27/146
Abstract: A dual mode focal plane array having a readout integrated circuit (IC) is provided herein that is electrically switchable between a first mode (e.g., direction injection mode) and a second mode (e.g., buffered direction injection) based in part on a level of a detection current. The IC includes a switching network disposed between an operational amplifier and a switching element to transition the IC between the first and second mode responsive to a control signal. The control signal can include instructions to open or close the one or more switches of the switching network and thus transition the IC between the different modes.
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公开(公告)号：US11557235B1
公开(公告)日：2023-01-17
申请号：US17644542
申请日：2021-12-15
Applicant: Raytheon Company
Inventor： Jehyuk Rhee , Bryan W. Kean , John L. Vampola
Abstract: A device includes multiple row power lines and multiple row control lines arranged in rows, where each row control line corresponds to one of the row power lines. The device also includes multiple column power lines arranged in columns. The device further includes multiple unit cells, where each unit cell is coupled to one of the row power lines and one of the row control lines and selectively coupled to one of the column power lines. In addition, the device includes multiple row power switches and multiple column power switches arranged in pairs, where each pair includes one of the row power switches and one of the column power switches. Each pair is configured to selectively (i) connect a corresponding one of the rows and a corresponding one of the columns or (ii) isolate the corresponding one row and the corresponding one column from each other.
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公开(公告)号：US20200029041A1
公开(公告)日：2020-01-23
申请号：US16040777
申请日：2018-07-20
Applicant: Raytheon Company
Inventor： Jehyuk Rhee
IPC: H04N5/378 , H04N5/3745 , H04N5/33
Abstract: A dual mode focal plane array having a readout integrated circuit (IC) is provided herein that is electrically switchable between a first mode (e.g., direction injection mode) and a second mode (e.g., buffered direction injection) based in part on a level of a detection current. The IC includes a switching network disposed between an operational amplifier and a switching element to transition the IC between the first and second mode responsive to a control signal. The control signal can include instructions to open or close the one or more switches of the switching network and thus transition the IC between the different modes.
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公开(公告)号：US12163844B2
公开(公告)日：2024-12-10
申请号：US17523391
申请日：2021-11-10
Applicant: RAYTHEON COMPANY
Inventor： Jehyuk Rhee , Matthew C. Thomas , Henry Lee
Abstract: A LADOR circuit is in signal communication with a pixel array. The LADOR circuit is configured to generate an integrator reset voltage based on a resistance of the at least one heated bolometer pixel, and to detect laser energy incident on the at least one heated bolometer pixel based on a comparison between the integrator reset voltage and an input threshold voltage (Vthreshold).
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Patent Agency Ranking
公开(公告)号：US20240288311A1
公开(公告)日：2024-08-29
申请号：US17523391
申请日：2021-11-10
Applicant: RAYTHEON COMPANY
Inventor： Jehyuk Rhee , Matthew C. Thomas , Henry Lee
CPC classification number: G01J5/24 , G01J5/048 , G01J2005/0077
Abstract: A LADOR circuit is in signal communication with a pixel array. The LADOR circuit is configured to generate an integrator reset voltage based on a resistance of the at least one heated bolometer pixel, and to detect laser energy incident on the at least one heated bolometer pixel based on a comparison between the integrator reset voltage and an input threshold voltage (Vthreshold).
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公开(公告)号：US12130185B2
公开(公告)日：2024-10-29
申请号：US17406432
申请日：2021-08-19
Applicant: RAYTHEON COMPANY
Inventor： Jehyuk Rhee , Henry Lee , Matthew C. Thomas
CPC classification number: G01J5/24 , G01J2005/0077 , G01J2005/202
Abstract: A trigger sense circuit includes a pseudo-differential comparator circuit in signal communication with a pixel array. The pseudo-differential comparator circuit includes a first input in signal communication with a reference pixel group included in the pixel array to receive a pixel reference voltage, and a second input in signal communication with a target pixel group included in the pixel array to receive a pixel target voltage. The pseudo-differential comparator circuit is configured to selectively operate in a calibration mode to remove false trigger events and a comparison mode to detect at least one overheated pixel included in the target pixel group.
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公开(公告)号：US20230056910A1
公开(公告)日：2023-02-23
申请号：US17406432
申请日：2021-08-19
Applicant: RAYTHEON COMPANY
Inventor： Jehyuk Rhee , Henry Lee , Matthew C. Thomas
IPC: G01J5/24
Abstract: A trigger sense circuit includes a pseudo-differential comparator circuit in signal communication with a pixel array. The pseudo-differential comparator circuit includes a first input in signal communication with a reference pixel group included in the pixel array to receive a pixel reference voltage, and a second input in signal communication with a target pixel group included in the pixel array to receive a pixel target voltage. The pseudo-differential comparator circuit is configured to selectively operate in a calibration mode to remove false trigger events and a comparison mode to detect at least one overheated pixel included in the target pixel group.
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公开(公告)号：US10917599B2
公开(公告)日：2021-02-09
申请号：US16040780
申请日：2018-07-20
Applicant: Raytheon Company
Inventor： Jehyuk Rhee , Angelika Kononenko , Christian M. Boemler
IPC: H04N5/378 , H04N5/33 , H04N5/3745
Abstract: Methods and apparatus for a dual mode focal plane array having a background module including a first capacitor to integrate a first signal for a first amount of time, wherein the first signal comprises a background signal, and a signal module including a second capacitor to integrate a second signal for a second amount of time, wherein the second signal comprises a signal of interest and the background signal, wherein the first and second capacitors have impedance values in a first ratio, and wherein the first amount of time and the second amount of time define a second ratio corresponding to the first ratio.
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公开(公告)号：US20200029042A1
公开(公告)日：2020-01-23
申请号：US16040780
申请日：2018-07-20
Applicant: Raytheon Company
Inventor： Jehyuk Rhee , Angelika Kononenko , Christian M. Boemler
IPC: H04N5/378 , H04N5/33 , H04N5/3745
Abstract: Methods and apparatus for a dual mode focal plane array having a background module including a first capacitor to integrate a first signal for a first amount of time, wherein the first signal comprises a background signal, and a signal module including a second capacitor to integrate a second signal for a second amount of time, wherein the second signal comprises a signal of interest and the background signal, wherein the first and second capacitors have impedance values in a first ratio, and wherein the first amount of time and the second amount of time define a second ratio corresponding to the first ratio.
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