公开(公告)号：US20240015889A1

公开(公告)日：2024-01-11

申请号：US18044789

申请日：2021-09-09

Applicant: RESONAC CORPORATION

Inventor： Kei TOGASAKI ,  Kenichi IWASHITA ,  Keishi ONO ,  Mao NARITA ,  Kazuyuki MITSUKURA ,  Masaya TOBA

IPC: H05K1/18 ,  H05K3/12 ,  H05K3/18 ,  H05K3/02

CPC classification number: H05K1/181 ,  H05K3/1208 ,  H05K3/181 ,  H05K3/022

Abstract: A method for producing a wiring board, including: a step of pretreating the surface of a metal layer exposed into an opening by bringing the surface into contact with a pretreatment liquid at a predetermined pretreatment temperature; and a step of forming a copper plating layer on the metal layer by electrolytic plating. The resist layer and the pretreatment liquid are selected such that a mass change rate of the resist layer when the resist layer before being exposed and developed is immersed in the pretreatment liquid is −2.0% by mass or more. The mass change rate is a value calculated by Expression: Mass change rate (% by mass)={(W1−W0)/W0}×100. W1 is the mass of the resist layer after a laminated body including a resist layer 3 and a copper foil is immersed in the pretreatment liquid at the pretreatment temperature for 30 minutes.

公开(公告)号：US20250142731A1

公开(公告)日：2025-05-01

申请号：US18837891

申请日：2023-02-15

Applicant: Resonac Corporation

Inventor： Kei TOGASAKI ,  Kenichi IWASHITA ,  Kensuke YOSHIHARA ,  Masaya TOBA

IPC: H05K3/18 ,  G03F1/38 ,  H05K1/02

Abstract: Provided is a method for manufacturing a wiring substrate. The method includes forming a resist layer on a support body, exposing the resist layer, developing the exposed resist layer to form an opening in the resist layer, forming a metal wiring in the opening, and removing the resist layer after the metal wiring is formed. In the exposing of the resist layer, a wiring exposure pattern that corresponds to the metal wiring, and a dummy exposure pattern that does not correspond to the metal wiring are exposed to the resist layer. At least a part of the dummy exposure pattern is located in a region within 200 μm from an end portion of the wiring exposure pattern.

公开(公告)号：US20240341039A1

公开(公告)日：2024-10-10

申请号：US18294158

申请日：2022-07-29

Applicant: Resonac Corporation

Inventor： Kei TOGASAKI ,  Kazuyuki MITSUKURA ,  Masaya TOBA ,  Kenichi IWASHITA ,  Keishi ONO ,  Mao NARITA

IPC: H05K3/10 ,  C25D3/38 ,  C25D5/00 ,  C25D5/02 ,  C25D7/12 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02

CPC classification number: H05K3/10 ,  C25D3/38 ,  C25D5/022 ,  C25D5/605 ,  C25D7/123 ,  H05K1/02 ,  H01L21/4846 ,  H01L23/49866 ,  H05K2203/11

Abstract: A method for manufacturing a wiring board, including: forming a resist layer on a seed layer comprising a metal provided on a support body; forming a pattern including an opening to which the seed layer is exposed in the resist layer by light exposure and development of the resist layer, and forming a copper plating layer on the seed layer exposed into the opening by electrolytic plating, in this order. The arithmetic mean roughness Ra of the surface of the seed layer on a side opposite to the support body is 0.05 μm or more and 0.30 μm or less.