公开(公告)号：US20240341039A1

公开(公告)日：2024-10-10

申请号：US18294158

申请日：2022-07-29

Applicant: Resonac Corporation

Inventor： Kei TOGASAKI ,  Kazuyuki MITSUKURA ,  Masaya TOBA ,  Kenichi IWASHITA ,  Keishi ONO ,  Mao NARITA

IPC: H05K3/10 ,  C25D3/38 ,  C25D5/00 ,  C25D5/02 ,  C25D7/12 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02

CPC classification number: H05K3/10 ,  C25D3/38 ,  C25D5/022 ,  C25D5/605 ,  C25D7/123 ,  H05K1/02 ,  H01L21/4846 ,  H01L23/49866 ,  H05K2203/11

Abstract: A method for manufacturing a wiring board, including: forming a resist layer on a seed layer comprising a metal provided on a support body; forming a pattern including an opening to which the seed layer is exposed in the resist layer by light exposure and development of the resist layer, and forming a copper plating layer on the seed layer exposed into the opening by electrolytic plating, in this order. The arithmetic mean roughness Ra of the surface of the seed layer on a side opposite to the support body is 0.05 μm or more and 0.30 μm or less.

公开(公告)号：US20240397635A1

公开(公告)日：2024-11-28

申请号：US18791515

申请日：2024-08-01

Applicant: RESONAC CORPORATION

Inventor： Masaya TOBA ,  Kazuyuki MITSUKURA

IPC: H05K3/38 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/18 ,  H05K3/46

Abstract: A method for manufacturing a wiring structure includes forming a wiring on an insulating resin layer, which includes forming a modified region including pores in a surface layer of the insulating resin layer by treating a surface of the insulating resin layer with a treatment method including surface modification; forming a seed layer on the surface of the insulating resin layer by sputtering; and forming the wiring on the seed layer by electrolytic copper plating. The method may include, in this order, forming a surface treatment agent layer that covers a surface of the wiring by treating the surface of the wiring with a surface treatment agent for improving adhesion; and forming a modified region including pores in a surface layer of a first layer of the insulating resin layer by treating the surface of the first layer of the insulating resin layer with a treatment method including surface modification.

公开(公告)号：US20240306308A1

公开(公告)日：2024-09-12

申请号：US18650160

申请日：2024-04-30

Applicant: RESONAC CORPORATION

Inventor： Masaya TOBA ,  Kazuhiko KURAFUCHI ,  Takashi MASUKO ,  Kazuyuki MITSUKURA ,  Shinichiro ABE

IPC: H05K3/18 ,  C23C18/16 ,  C23C18/20 ,  C23C18/32 ,  C23C18/38 ,  H05K1/03

CPC classification number: H05K3/181 ,  C23C18/1605 ,  C23C18/165 ,  C23C18/20 ,  C23C18/32 ,  C23C18/38 ,  H05K1/032 ,  H05K2201/068

Abstract: A semiconductor package includes a wiring board and a semiconductor element mounted on the wiring board. The wiring board includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring. The metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass.

公开(公告)号：US20240088051A1

公开(公告)日：2024-03-14

申请号：US18261114

申请日：2022-01-12

Applicant: Resonac Corporation

Inventor： Kazuyuki MITSUKURA ,  Shunsuke OTAKE ,  Hiroaki FUJITA ,  Shinji SHIMAOKA ,  Takashi MASUKO ,  Kazuhiko KURAFUCHI

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4846 ,  H01L24/08 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/561 ,  H01L2224/08225 ,  H01L2224/19 ,  H01L2224/211

Abstract: A method for manufacturing a semiconductor device is disclosed. The method for manufacturing a semiconductor device includes preparing a base material, preparing a plurality of semiconductor elements each having a connection terminal, preparing a wiring board provided with a first wiring, arranging the plurality of semiconductor elements on the base material, covering the plurality of semiconductor elements on the base material with an insulating material, arranging the wiring board on at least one of the plurality of semiconductor elements so that the first wiring is connected to at least some of the connection terminals of the plurality of semiconductor elements covered with the insulating material, and forming a second wiring around the first wiring. The first wiring has finer wiring than the second wiring.

公开(公告)号：US20240015889A1

公开(公告)日：2024-01-11

申请号：US18044789

申请日：2021-09-09

Applicant: RESONAC CORPORATION

Inventor： Kei TOGASAKI ,  Kenichi IWASHITA ,  Keishi ONO ,  Mao NARITA ,  Kazuyuki MITSUKURA ,  Masaya TOBA

IPC: H05K1/18 ,  H05K3/12 ,  H05K3/18 ,  H05K3/02

CPC classification number: H05K1/181 ,  H05K3/1208 ,  H05K3/181 ,  H05K3/022

Abstract: A method for producing a wiring board, including: a step of pretreating the surface of a metal layer exposed into an opening by bringing the surface into contact with a pretreatment liquid at a predetermined pretreatment temperature; and a step of forming a copper plating layer on the metal layer by electrolytic plating. The resist layer and the pretreatment liquid are selected such that a mass change rate of the resist layer when the resist layer before being exposed and developed is immersed in the pretreatment liquid is −2.0% by mass or more. The mass change rate is a value calculated by Expression: Mass change rate (% by mass)={(W1−W0)/W0}×100. W1 is the mass of the resist layer after a laminated body including a resist layer 3 and a copper foil is immersed in the pretreatment liquid at the pretreatment temperature for 30 minutes.

公开(公告)号：US20230331946A1

公开(公告)日：2023-10-19

申请号：US18245347

申请日：2021-09-15

Applicant: Resonac Corporation

Inventor： Shunsuke OTAKE ,  Kazuyuki MITSUKURA ,  Shinji SHIMAOKA ,  Hiroaki FUJITA ,  Masaki TAKAHASHI

IPC: C08J5/24 ,  H01L23/498 ,  H01L21/48 ,  B32B15/14

CPC classification number: C08J5/244 ,  H01L23/49822 ,  H01L23/49894 ,  H01L21/4857 ,  B32B15/14 ,  C08J2379/08 ,  C08J2463/00 ,  B32B2307/7376 ,  B32B2457/00 ,  B32B2260/021 ,  B32B2260/046

Abstract: A method for manufacturing a substrate material for a semiconductor package, including a step of increasing a temperature of a laminated body in which a metal foil, one or more prepregs, and a metal foil are laminated in this order to a hot-press temperature while pressurizing the laminated body. The prepreg contains an inorganic fiber base material and a thermosetting resin composition. A content of the thermosetting resin composition is 40 to 80% by mass on the basis of a mass of the prepreg. In the step of increasing the temperature of the laminated body to the hot-press temperature while pressurizing the laminated body, the laminated body is heated in a condition in which the lowest melt viscosity of the prepreg is 5000 Pa·s or less.

公开(公告)号：US20230253215A1

公开(公告)日：2023-08-10

申请号：US18017954

申请日：2020-07-28

Applicant: Resonac Corporation

Inventor： Masaya TOBA ,  Kazuhiko KURAFUCHI ,  Takashi MASUKO ,  Kazuyuki MITSUKURA

IPC: H01L21/48 ,  H01L23/498 ,  C25D7/12 ,  C25D5/48 ,  C25D5/02 ,  C23C18/16 ,  C23C28/02

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  C25D7/123 ,  C25D5/48 ,  C25D5/022 ,  C23C18/1653 ,  C23C28/023 ,  C23C18/38

Abstract: A method for producing a wiring board according to the present disclosure includes: (A) forming a first insulating material layer on a supporting substrate; (B) forming a first opening part in the first insulating material layer; (C) forming a seed layer on the first insulating material layer; (D) providing a resist pattern on a surface of the seed layer; (E) forming a wiring part including a pad and wiring; (F) removing the resist pattern; (G) removing the seed layer; (H) applying a first surface treatment to the surface of the pad; (I) forming a second insulating material layer; (J) forming a second opening part in the second insulating material layer; (K) applying a second surface treatment to the surface of the pad; and (L) heating the second insulating material layer to a temperature equal to or higher than the glass transition temperature of the second insulating material layer.

公开(公告)号：US20250105205A1

公开(公告)日：2025-03-27

申请号：US18716993

申请日：2021-12-08

Applicant: Resonac Corporation

Inventor： Yuki IMAZU ,  Kazuyuki MITSUKURA

IPC: H01L23/00

Abstract: A method for manufacturing a laminate includes forming a first organic insulating layer including a first thermosetting resin and first inorganic oxide particles on a first support substrate, polishing a first surface of the first organic insulating layer to planarize the first surface, and bonding the polished first surface to a second surface of a second organic insulating layer including a second thermosetting resin and second inorganic oxide particles.

公开(公告)号：US20240049395A1

公开(公告)日：2024-02-08

申请号：US18258556

申请日：2020-12-25

Applicant: Resonac Corporation

Inventor： Masaya TOBA ,  Kazuyuki MITSUKURA ,  Masaki YAMAGUCHI

IPC: H05K1/18 ,  H05K3/02

CPC classification number: H05K1/181 ,  H05K3/022 ,  H05K2201/10553 ,  H05K2201/0358 ,  H05K2203/1377 ,  H05K2201/0209

Abstract: A layered plate including a copper layer having a thickness of 5 μm or less, and a resin layer provided on a surface of the copper layer, in which a water absorption rate of the resin layer is 1% or less after being left in an environment of 130° C. in temperature and 85% in relative humidity for 200 hours.

公开(公告)号：US20230356498A1

公开(公告)日：2023-11-09

申请号：US18245348

申请日：2021-09-15

Applicant: Resonac Corporation

Inventor： Shunsuke OTAKE ,  Kazuyuki MITSUKURA ,  Takashi MASUKO ,  Kazuhiko KURAFUCHI ,  Shinji SHIMAOKA ,  Hiroaki FUJITA

IPC: B32B5/26 ,  B32B33/00

CPC classification number: B32B5/263 ,  B32B33/00 ,  B32B2260/023 ,  B32B2260/046 ,  B32B2457/00

Abstract: An organic core material including a first layer having a first fiber cloth and a first resin layer formed from a first resin component and having the first fiber cloth embedded therein, and a second layer having a second fiber cloth and a second resin layer formed from a second resin component and having the second fiber cloth embedded therein. The organic core material has a laminated structure including the second layer, a plurality of the first layers, and the second layer in order, and a content percentage of the second resin component based on a mass of the second resin layer is higher than a content percentage of the first resin component based on a mass of the first resin layer.