公开(公告)号：US20060255474A1

公开(公告)日：2006-11-16

申请号：US11444894

申请日：2006-06-01

Applicant: Nazir Ahmad ,  Young-Do Kweon ,  Samuel Tam ,  Kyung-Moon Kim ,  Rajendra Pendse

Inventor： Nazir Ahmad ,  Young-Do Kweon ,  Samuel Tam ,  Kyung-Moon Kim ,  Rajendra Pendse

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/10135 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. In some embodiments the metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.

公开(公告)号：US20050098886A1

公开(公告)日：2005-05-12

申请号：US10983898

申请日：2004-11-08

Applicant: Rajendra Pendse

Inventor： Rajendra Pendse

IPC: H01L21/60 ,  H01L23/498 ,  H01L23/50 ,  H01L23/48

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract translation: 倒装芯片互连焊盘布局将芯片信号焊盘布置在靠近裸片周边的裸片表面上，并且芯片功率和接地焊盘从信号焊盘上排列在芯片表面上; 并且具有以与芯片焊盘布局互补的方式布置的相应封装衬底上的信号焊盘，并且信号线从模具边缘下方的信号焊盘远离管芯封装路由，并且将电源和接地线路由到下面的通孔 模具占地面积。 此外，倒装芯片半导体封装，其中倒装芯片互连焊盘布局具有位于管芯的边缘部分中的管芯信号焊盘以及从信号焊盘排列在管芯表面上的管芯电源和接地焊盘以及相应的封装 衬底具有以与芯片焊盘布局互补的方式布置的信号焊盘，并且信号线从模具边缘下方的信号焊盘路由远离管芯封装。

公开(公告)号：US20050056944A1

公开(公告)日：2005-03-17

申请号：US10960893

申请日：2004-10-07

Applicant: Rajendra Pendse ,  Samuel Tam

Inventor： Rajendra Pendse ,  Samuel Tam

IPC: H01L23/12 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/18 ,  H01L23/52

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/16 ,  H01L24/48 ,  H01L2223/6627 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8383 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/1903 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package achieves miniaturization and excellent high-speed operation by employing flip chip interconnection between the die and the package substrate, and mounting the chip on the same side of the package substrate as the solder balls for the second level interconnection to the printed circuit board. Also, two-die packages have a first die attached to the same surface as the second level interconnect structures and connected using flip chip interconnection, and a second die connected to the opposite surface of the substrate and interconnected either by wire bonding or by flip chip interconnection.

Abstract translation: 芯片封装通过在芯片和封装基板之间采用倒装芯片互连，并且将芯片安装在封装基板的与印刷电路板的第二级互连的焊球相同的一侧上，实现了小型化和优异的高速操作 。 此外，双管芯封装具有附接到与第二级互连结构相同的表面并且使用倒装芯片互连连接的第一管芯，以及连接到衬底的相对表面并通过引线接合或通过倒装芯片互连的第二管芯 互连。

公开(公告)号：US20060255473A1

公开(公告)日：2006-11-16

申请号：US11435555

申请日：2006-05-16

Applicant: Rajendra Pendse

Inventor： Rajendra Pendse

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H05K3/3452 ,  H01L21/4846 ,  H01L21/4853 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/11822 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/0989 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the remelt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

Abstract translation: 用于倒装芯片互连的焊接掩模具有跨越多个电路元件的公共开口。 焊接掩模允许在互连的重熔阶段期间焊料的限制，但是在焊接掩模图案化的通用设计规则中。 此外，用于倒装芯片布线的基板包括具有跨越多个电路元件的公共开口的基板。 此外，倒装芯片封装包括具有跨越多个电路元件的公共开口的基板。

公开(公告)号：US20060170093A1

公开(公告)日：2006-08-03

申请号：US11372755

申请日：2006-03-10

Applicant: Rajendra Pendse

Inventor： Rajendra Pendse

IPC: H01L23/52

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

公开(公告)号：US20060163715A1

公开(公告)日：2006-07-27

申请号：US11372989

申请日：2006-03-10

Applicant: Rajendra Pendse

Inventor： Rajendra Pendse

IPC: H01L23/52

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

公开(公告)号：US20070241464A1

公开(公告)日：2007-10-18

申请号：US11640534

申请日：2006-12-14

Applicant: Rajendra Pendse ,  KyungOe Kim ,  Taewoo Kang

Inventor： Rajendra Pendse ,  KyungOe Kim ,  Taewoo Kang

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.

Abstract translation: 倒装芯片互连具有渐缩的互连结构，并且互连结构与衬底金属化部位的接触面积小于互连结构与管芯焊盘的接触面积。 焊接掩模在互连部位上具有开口，并且焊料掩模在开口边缘处与互连结构接触或者接近互连结构。 倒装芯片互连设置有底部填充。 在底部填充过程中，具有互连结构的焊接掩模的接触（或接近）干扰了底部填充材料朝向邻近现场的衬底的流动，导致形成由底部填充物未填充的空隙，邻近接触 该互连结构与衬底上的部位金属化。 该空隙可以帮助缓解由系统温度变化引起的应变。

公开(公告)号：US20070158820A1

公开(公告)日：2007-07-12

申请号：US11306808

申请日：2006-01-11

Applicant: Rajendra Pendse

Inventor： Rajendra Pendse

IPC: H01L23/12

CPC classification number: H01L21/563 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00012

Abstract: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond finger, and a portion of the pedestal are embedded in an resin layer with an exposed portion of the pedestal protruding from the resin layer. A second die is mounted on the first die and electrically coupled to the exposed portion of the pedestal.

Abstract translation: 一种集成电路封装系统，包括提供其上具有接合指状物的衬底，并在接合指的一部分上形成基座。 第一管芯安装在衬底上并与粘结指状物相邻。 第一模具的一部分，粘结指状物的一部分和基座的一部分嵌入树脂层中，底座的暴露部分从树脂层突出。 第二管芯安装在第一管芯上并电耦合到基座的暴露部分。

公开(公告)号：US20070105277A1

公开(公告)日：2007-05-10

申请号：US11640468

申请日：2006-12-14

Applicant: Rajendra Pendse ,  KyungOe Kim ,  Taewoo Kang

Inventor： Rajendra Pendse ,  KyungOe Kim ,  Taewoo Kang

IPC: H01L21/00 ,  H01L23/48

CPC classification number: H01L21/563 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.

Abstract translation: 倒装芯片互连具有渐缩的互连结构，并且互连结构与衬底金属化部位的接触面积小于互连结构与管芯焊盘的接触面积。 此外，接触焊盘互连的小区域上的引线键合或窄键焊接或键合包括这种锥形倒装芯片互连。 此外，用于制造互连结构的方法包括提供具有互连焊盘的管芯，提供在图案化导电层上具有互连位置的衬底，在管芯焊盘上提供凸块，在互连位置处或在互连位置上提供可熔电导材料 碰撞，将凸块配合到互连部位，并加热熔化可熔材料。

公开(公告)号：US20060216860A1

公开(公告)日：2006-09-28

申请号：US11388755

申请日：2006-03-24

Applicant: Rajendra Pendse

Inventor： Rajendra Pendse

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.