公开(公告)号：US09778960B2

公开(公告)日：2017-10-03

申请号：US14390423

申请日：2012-06-29

Applicant: Kimon Berlin ,  Tom Fisher ,  Raphael Gay

Inventor： Kimon Berlin ,  Tom Fisher ,  Raphael Gay

IPC: G06F9/50 ,  G06F1/20 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/329 ,  G06F9/4856 ,  G06F9/5038 ,  Y02D10/22 ,  Y02D10/24

Abstract: Implementations disclosed herein relate to thermal based prioritized computing application scheduling. For example, a processor may determine a prioritized computing application. The processor may schedule the prioritized computing application to transfer execution from a first processing unit to a second processing unit based on a thermal reserve energy associated with the second processing unit.

公开(公告)号：US20120260015A1

公开(公告)日：2012-10-11

申请号：US13082282

申请日：2011-04-07

Applicant: Raphael Gay ,  Robert J. Horning ,  Robert Bohl ,  Brooke Melinda O'Dell Loader

Inventor： Raphael Gay ,  Robert J. Horning ,  Robert Bohl ,  Brooke Melinda O'Dell Loader

IPC: G06F13/14

CPC classification number: G06F13/409 ,  G06F2213/0026

Abstract: Peripheral Component Interconnect Express (“PCIe”) Port bifurcation systems and methods are provided. An illustrative PCIe port bifurcation card can include: a PCIe interface and a plurality of PCIe devices, each independently coupled to the interface via an unswitched connection. The card can further include a read only memory (ROM) coupled to the interface, the ROM can include bifurcation data. A clocking signal replicator can be coupled to the interface to: replicate a reference clock signal received via the interface and provide the replicated reference dock signal to each of the plurality of PCIe devices.

Abstract translation: 提供外围组件互连Express（PCIe）端口分岔系统和方法。 说明性的PCIe端口分叉卡可以包括：PCIe接口和多个PCIe设备，每个PCIe设备经由非切换的连接独立地耦合到接口。 卡还可以包括耦合到接口的只读存储器（ROM），ROM可以包括分岔数据。 时钟信号复制器可以耦合到接口以：复制经由接口接收的参考时钟信号，并将复制的参考基站信号提供给多个PCIe设备中的每一个。

公开(公告)号：US07362589B2

公开(公告)日：2008-04-22

申请号：US11037596

申请日：2005-01-18

Applicant: Raphael Gay

Inventor： Raphael Gay

IPC: H01R12/16

CPC classification number: G06F1/185 ,  G06F13/409 ,  H05K1/0295 ,  H05K1/111 ,  H05K3/366 ,  H05K2201/044 ,  H05K2201/09954 ,  H05K2201/10189

Abstract: A circuit board comprising at least one slot provided on a surface of the circuit board. An add-in card can be mated to the slot. The slot comprises a first electrical connection adapted to couple to an add-in card of a first type and a second electrical connection adapted to couple to an add-in card of a second type. The first or second types of add-in cards are different.

Abstract translation: 一种电路板，包括设置在电路板的表面上的至少一个槽。 附加卡可以与插槽配合使用。 插槽包括适于耦合到第一类型的附加卡的第一电连接和适于耦合到第二类型的附加卡的第二电连接。 第一或第二类附加卡是不同的。

公开(公告)号：US10140231B2

公开(公告)日：2018-11-27

申请号：US14374681

申请日：2012-01-31

Applicant: Jonathan D. Bassett ,  Raphael Gay ,  Linden H. McClure

Inventor： Jonathan D. Bassett ,  Raphael Gay ,  Linden H. McClure

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: Example embodiments disclosed herein relate to configuring a flexible port. The configuration of a computing device is detected based on a coupling of an interface to a flexible input/output port. The flexible input/output port is configured based on the detected configuration of the computing device.

公开(公告)号：US07898817B2

公开(公告)日：2011-03-01

申请号：US11581854

申请日：2006-10-17

Applicant: Raphael Gay

Inventor： Raphael Gay

IPC: H05K7/00

CPC classification number: G06F17/3048

Abstract: In one embodiment, a circuit board assembly comprises a first circuit board comprising a first array of alignment holes, a second circuit board comprising a second array of alignment holes, and at least one press pin dimensioned to fit in one or more of the alignment holes.

Abstract translation: 在一个实施例中，电路板组件包括第一电路板，第一电路板包括第一阵列的对准孔，第二电路板，其包括第二阵列的对准孔，以及至少一个压销，其尺寸适于装配在一个或多个对准孔 。

公开(公告)号：US20150067692A1

公开(公告)日：2015-03-05

申请号：US14390423

申请日：2012-06-29

Applicant: Kimon Berlin ,  Tom Fisher ,  Raphael Gay

Inventor： Kimon Berlin ,  Tom Fisher ,  Raphael Gay

IPC: G06F9/50

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/329 ,  G06F9/4856 ,  G06F9/5038 ,  Y02D10/22 ,  Y02D10/24

Abstract: Implementations disclosed herein relate to thermal based prioritized computing application scheduling. For example, a processor may determine a prioritized computing application. The processor may schedule the prioritized computing application to transfer execution from a first processing unit to a second processing unit based on a thermal reserve energy associated with the second processing unit.

Abstract translation: 本文公开的实现涉及基于热的优先级计算应用调度。 例如，处理器可以确定优先级计算应用。 处理器可以基于与第二处理单元相关联的热储备能量来安排优先计算应用程序将执行从第一处理单元传送到第二处理单元。

公开(公告)号：US20130173901A1

公开(公告)日：2013-07-04

申请号：US13821506

申请日：2010-11-01

Applicant: Raphael Gay ,  Robert J. Horning

Inventor： Raphael Gay ,  Robert J. Horning

IPC: G06F9/44

CPC classification number: G06F9/4405 ,  G06F13/12 ,  G06F13/4068

Abstract: Multi-processor computer systems and methods are provided. A multi-processor computer system can include a plurality of communicatively coupled processors (1101-N), each coupled to a common motherboard (120) and each associated with a memory (1401-N). The system can include a boot code (130) executable from at least one of a standard mode and an independent mode. The plurality of communicatively coupled processors can execute one instance of the boot code in standard mode and at least a portion of the plurality of communicatively coupled processors can execute one instance of the boot code in independent mode.

Abstract translation: 提供多处理器计算机系统和方法。 多处理器计算机系统可以包括多个通信耦合处理器（1101-N），每个处理器耦合到公共母板（120），并且每个处理器与存储器（1401-N）相关联。 该系统可以包括可从标准模式和独立模式中的至少一个执行的引导代码（130）。 多个通信耦合的处理器可以以标准模式执行引导代码的一个实例，并且多个通信耦合的处理器的至少一部分可以以独立模式执行引导代码的一个实例。

公开(公告)号：US07467252B2

公开(公告)日：2008-12-16

申请号：US10629940

申请日：2003-07-29

Applicant: Charles Hartman ,  Raphael Gay

Inventor： Charles Hartman ,  Raphael Gay

IPC: G06F13/00 ,  G06F13/36 ,  G03G15/01

CPC classification number: G06F13/4068 ,  G06F13/4022

Abstract: An I/O bus architecture is configurable so that I/O bandwidth may be re-allocated from one I/O slot or device to another. A first intermediate bus couples a system bus interface device to a first I/O bus interface device. A second intermediate bus couples the system bus interface device to a switching device. The switching device functions to couple the second intermediate bus either to the first or to the second I/O bus interface device responsive to a steering signal. The steering signal may be configured to indicate whether or not an I/O device is coupled to the second I/O bus interface device. If so, then the second intermediate bus is coupled to the second I/O bus interface device; but if not, it is coupled to the first I/O bus interface device so that the first I/O bus interface device may utilize the extra I/O bandwidth not being used by the second I/O bus interface device.

Abstract translation: I / O总线架构是可配置的，以便I / O带宽可以从一个I / O插槽或设备重新分配到另一个。 第一中间总线将系统总线接口设备耦合到第一I / O总线接口设备。 第二中间总线将系统总线接口设备耦合到交换设备。 开关装置用于响应于转向信号而将第二中间总线耦合到第一或第二I / O总线接口装置。 转向信号可以被配置为指示I / O设备是否耦合到第二I / O总线接口设备。 如果是这样，则第二中间总线耦合到第二I / O总线接口设备; 但是如果不是，则它耦合到第一I / O总线接口设备，使得第一I / O总线接口设备可以利用第二I / O总线接口设备未使用的额外的I / O带宽。

公开(公告)号：US20080117588A1

公开(公告)日：2008-05-22

申请号：US11600977

申请日：2006-11-17

Applicant: Raphael Gay ,  Christine Lin

Inventor： Raphael Gay ,  Christine Lin

IPC: G06F1/16 ,  H05K1/18 ,  H05K7/20 ,  A47B81/00

CPC classification number: G06F1/185 ,  G06F1/18 ,  G06F1/20

Abstract: In one embodiment, a computer system comprises at least one input/output device, and a motherboard designed in compliance with an ATX form factor standard and comprising eight slots to receive input/output cards.

公开(公告)号：US20060080484A1

公开(公告)日：2006-04-13

申请号：US10960530

申请日：2004-10-07

Applicant: Joel Lefebvre ,  Raphael Gay ,  Stephen Uhlmann

Inventor： Joel Lefebvre ,  Raphael Gay ,  Stephen Uhlmann

IPC: G06F13/00

CPC classification number: G06F15/16

Abstract: A system comprises a plurality of processor sockets and a module adapted to be received into at least one of the processor sockets in place of a processor. The sockets are electrically connected by way of communication links. Each socket has a plurality of electrical contacts electrically connected to the communication links. The module has electrical contacts that electrically mate with the contacts of the socket to thereby electrically connect together at least two of the communication links.

Abstract translation: 系统包括多个处理器插座和适于被接收到处理器插槽中的至少一个代替处理器的模块。 插座通过通信链路电连接。 每个插座具有电连接到通信链路的多个电触点。 该模块具有与插座的触头电配合的电触头，从而将至少两个通信链路电连接在一起。