公开(公告)号：US20240248684A1

公开(公告)日：2024-07-25

申请号：US18404789

申请日：2024-01-04

Applicant: Renesas Electronics Corporation

Inventor： Shuji SENDA ,  Katsumi TOGAWA

IPC: G06F7/544 ,  G06F1/3234 ,  G06F7/487 ,  G06F7/509 ,  G06N3/063

CPC classification number: G06F7/5443 ,  G06F1/3234 ,  G06F7/4876 ,  G06F7/5095 ,  G06N3/063

Abstract: A semiconductor device according to one includes: an initial value setting unit configured to provide an initial value of a register that holds a cumulative value to be a result of a product-sum operation in a product-sum operation circuit; and an initial value canceling circuit configured to cancel the initial value contained in the cumulative value held by the register and output a final output value, and the initial value setting unit sets a positive or negative value other than zero as the initial value.

公开(公告)号：US20220004363A1

公开(公告)日：2022-01-06

申请号：US17358579

申请日：2021-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Katsumi TOGAWA ,  Teruhito TANAKA ,  Takao TOI

IPC: G06F7/544 ,  G06F7/53 ,  G06F17/16

Abstract: A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.

公开(公告)号：US20220129247A1

公开(公告)日：2022-04-28

申请号：US17569135

申请日：2022-01-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Takao TOI ,  Teruhito TANAKA ,  Katsumi TOGAWA

IPC: G06F7/544 ,  G06F17/16

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

公开(公告)号：US20160371147A1

公开(公告)日：2016-12-22

申请号：US15141687

申请日：2016-04-28

Applicant: Renesas Electronics Corporation

Inventor： Yoshitaka IZAWA ,  Katsumi TOGAWA ,  Takao TOI ,  Taro FUJII

IPC: G06F11/14

CPC classification number: G06F11/142 ,  G06F11/00 ,  G06F11/20 ,  G06F11/202 ,  G06F2201/805 ,  G06F2201/85

Abstract: According to an embodiment, a reconfigurable device 1 includes a configuration information storage memory 12, a state transition management unit 11, and a data path unit 13. When a failure is not detected in either of tiles T1 and T2 provided in the data path unit 13, the state transition management unit 11 selects the configuration information item so that a first processing circuit is configured using the tiles T1 and T2, while when a failure is detected in the tile T2, the state transition management unit 11 selects the configuration information item so that after a first intermediate processing circuit is configured using the tile T1 in which no failure is detected, a second intermediate processing circuit is configured again using the tile T1 in order to achieve the first processing circuit.

Abstract translation: 根据实施例，可重新配置设备1包括配置信息存储器12，状态转换管理单元11和数据路径单元13.当在数据路径单元中提供的片T1和T2中的任一个中未检测到故障时 如图13所示，状态转移管理单元11选择配置信息项，使得使用瓦片T1和T2配置第一处理电路，而当在瓦片T2中检测到故障时，状态转换管理单元11选择配置信息项 使得在使用未检测到故障的瓦片T1配置第一中间处理电路之后，使用瓦片T1再次配置第二中间处理电路，以实现第一处理电路。

公开(公告)号：US20210117352A1

公开(公告)日：2021-04-22

申请号：US17065169

申请日：2020-10-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Teruhito TANAKA ,  Katsumi TOGAWA ,  Takao TOI

IPC: G06F13/28

Abstract: A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

公开(公告)号：US20190384574A1

公开(公告)日：2019-12-19

申请号：US16410825

申请日：2019-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Takao TOI ,  Teruhito TANAKA ,  Katsumi TOGAWA

IPC: G06F7/544 ,  G06F17/16

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

公开(公告)号：US20180322010A1

公开(公告)日：2018-11-08

申请号：US16035055

申请日：2018-07-13

Applicant: Renesas Electronics Corporation

Inventor： Yoshitaka IZAWA ,  Katsumi TOGAWA ,  Takao TOI ,  Taro FUJII

IPC: G06F11/14 ,  G06F11/00 ,  G06F11/20

CPC classification number: G06F11/142 ,  G06F11/00 ,  G06F11/20 ,  G06F11/202 ,  G06F2201/805 ,  G06F2201/85

Abstract: A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.