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    METHOD OF MANUFACTURING WIRING SUBSTRATE
    1.
    发明申请
    METHOD OF MANUFACTURING WIRING SUBSTRATE 审中-公开

    公开(公告)号：US20180151486A1

    公开(公告)日：2018-05-31

    申请号：US15810578

    申请日：2017-11-13

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Kazuhiro KOBAYASHI ,  Yusuke KARASAWA

    IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683

    CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2221/68345 ,  H01L2221/68359

    Abstract: A method of manufacturing a wiring substrate includes providing a support that includes a support substrate and first and second metal layers stacked in order over the support substrate. A surface of the second metal layer facing away from the first metal layer is a roughened surface or formed of particles. The second metal layer is selectively etchable with respect to the first metal layer. The method further includes selectively forming a third metal layer on the surface of the second metal layer, forming a first wiring layer that is a laminate of the second and third metal layers by simultaneously roughening the third metal layer and dissolving the second metal layer not covered with the third metal layer using an etchant, forming an insulating layer that covers the first wiring layer on the first metal layer, removing the support substrate, and removing the first metal layer by etching.

    WIRING BOARD AND MOUNTING STRUCTURE
    3.
    发明申请
    WIRING BOARD AND MOUNTING STRUCTURE 审中-公开
    接线板和安装结构

    公开(公告)号：US20130314886A1

    公开(公告)日：2013-11-28

    申请号：US13892402

    申请日：2013-05-13

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Kazuhiro KOBAYASHI ,  Junichi Nakamura

    IPC: H05K1/11

    CPC classification number: H05K1/112 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0367 ,  H05K2203/0113 ,  H01L2924/00

    Abstract: A wiring board includes an insulating layer; a connection part provided on a surface of the insulating layer, the connection part including a first plating layer including a flat surface and a curved surface continuous with the flat surface, wherein the flat surface and the curved surface are exposed on the insulating layer, and an end portion of the curved surface is in contact with the surface of the insulating layer; and a second plating layer formed on an interior surface of the first plating layer so as to be coated with the first plating layer; and a via formed in the insulating layer so as to be connected to the second plating layer.

    Abstract translation: 布线板包括绝缘层; 所述连接部设置在所述绝缘层的表面上，所述连接部包括包括平坦表面的第一镀层和与所述平坦表面连续的弯曲表面，其中所述平坦表面和所述弯曲表面暴露在所述绝缘层上，以及 弯曲表面的端部与绝缘层的表面接触; 以及第二镀层，形成在所述第一镀层的内表面上以被涂覆有所述第一镀层; 以及形成在绝缘层中以与第二镀层连接的通孔。

    Wiring Substrate and Semiconductor Device
    7.
    发明申请
    Wiring Substrate and Semiconductor Device 有权
    接线基板和半导体器件

    公开(公告)号：US20160081194A1

    公开(公告)日：2016-03-17

    申请号：US14848453

    申请日：2015-09-09

    Applicant: Shinko Electric Industries Co., Ltd.

    Inventor： Junji Sato ,  Kiyotaka Mochizuki ,  Kazuhiro KOBAYASHI ,  Katsuya FUKASE

    IPC: H05K1/18 ,  H05K1/02

    CPC classification number: H05K3/4697 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4652 ,  H05K2201/10015 ,  H01L2924/00

    Abstract: A wiring substrate includes a core, a first wiring layer formed on a first surface of the core, and a second wiring layer formed on a second surface of the core. The first wiring layer includes a first opening, and the second wiring layer includes a second opening. The core includes a plurality of electronic component accommodating bores that extend through the core at portions exposed from the first and second openings. An electronic component is arranged in each electronic component accommodating bore. The electronic component accommodating bores are filled with an insulating layer. The core includes a partition located between adjacent electronic component accommodating bores. The partition is formed by part of the core.

    Abstract translation: 布线基板包括芯，形成在芯的第一表面上的第一布线层和形成在芯的第二表面上的第二布线层。 第一布线层包括第一开口，第二布线层包括第二开口。 芯包括多个电子部件容纳孔，其在从第一和第二开口露出的部分处延伸穿过芯。 每个电子部件容纳孔中布置有电子部件。 电子元件容纳孔被绝缘层填充。 芯部包括位于相邻的电子部件容纳孔之间的分隔件。 隔板由芯的一部分形成。

    WIRING SUBSTRATE
    8.
    发明申请
    WIRING SUBSTRATE 审中-公开
    接线基板

    公开(公告)号：US20140097009A1

    公开(公告)日：2014-04-10

    申请号：US14038190

    申请日：2013-09-26

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Kentaro KANEKO ,  Kazuhiro KOBAYASHI

    IPC: H05K1/02

    CPC classification number: H05K1/0296 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0346 ,  H05K2203/0554 ,  H01L2924/00012

    Abstract: A wiring substrate includes a first wiring layer, a first insulating layer, a second wiring layer, and a first wiring pattern. The second wiring layer includes a first metal foil that is thinner than the first wiring layer. A first via in the first insulating layer connects the first and second wiring layers. The first via is arranged to fill a first through hole and a first recess. The first through hole extends through the first insulating layer and has a first open end with a first opening diameter and a second open end with a smaller second opening diameter. The first recess is in communication with the first through hole. The first recess has a larger diameter than the second opening diameter. The first metal foil includes a first opening communicating with the first through hole and having a larger opening diameter larger than the first opening diameter.

    Abstract translation: 布线基板包括第一布线层，第一绝缘层，第二布线层和第一布线图案。 第二布线层包括比第一布线层薄的第一金属箔。 第一绝缘层中的第一通孔连接第一和第二布线层。 第一通孔布置成填充第一通孔和第一凹槽。 第一通孔延伸穿过第一绝缘层，并且具有第一开口直径的第一开口端和具有较小的第二开口直径的第二开口端。 第一凹槽与第一通孔连通。 第一凹部具有比第二开口直径更大的直径。 第一金属箔包括与第一通孔连通并且具有比第一开口直径大的开口直径的第一开口。

    WIRING SUBSTRATE
    9.
    发明申请
    WIRING SUBSTRATE 有权
    接线基板

    公开(公告)号：US20140076614A1

    公开(公告)日：2014-03-20

    申请号：US14021110

    申请日：2013-09-09

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Kazuhiro KOBAYASHI ,  Kotaro KODANI ,  Junichi NAKAMURA ,  Kentaro KANEKO

    IPC: H05K1/02

    CPC classification number: H05K1/0298 ,  H05K3/108 ,  H05K3/4682 ,  H05K2201/09563 ,  H05K2203/0152

    Abstract: A wiring substrate includes a first insulating layer, an adhesion insulating layer formed under the first insulating layer and an outer face of the adhesion insulating layer is made to a roughened face, a first wiring layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer, and in which a first via hole reaching the first wiring layer is provided, a second wiring layer formed on the second insulating layer, and connected to the first wiring layer through the first via hole, a second via hole formed in the adhesion insulating layer and the first insulating layer, and reaching the first wiring layer, and a third wiring layer formed on the outer face of the adhesion insulating layer, and connected to the first wiring layer through the second via hole.

    Abstract translation: 布线基板包括第一绝缘层，形成在第一绝缘层下方的粘合绝缘层和粘合绝缘层的外表面，粗糙面，形成在第一绝缘层上的第一布线层，第二绝缘层 形成在第一绝缘层上，并且其中提供到达第一布线层的第一通孔，形成在第二绝缘层上的第二布线层，并且通过第一通孔连接到第一布线层，第二通孔 形成在所述粘合绝缘层和所述第一绝缘层中，并到达所述第一布线层，以及形成在所述粘合绝缘层的外表面上的第三布线层，并且通过所述第二通孔与所述第一布线层连接。

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