公开(公告)号：US20150249075A1

公开(公告)日：2015-09-03

申请号：US14714421

申请日：2015-05-18

Applicant: SK hynix Inc.

Inventor： In Chul HWANG ,  Jae Myun KIM ,  Seung Jee KIM ,  Jin Su LEE

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/81191 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/81

Abstract: Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.

Abstract translation: 提供双层结构半导体芯片。 半导体芯片包括接合到第一半导体芯片的第一半导体芯片和第二半导体芯片。 第一半导体芯片包括具有第一底表面的第一基板。 第二半导体芯片包括具有第二底面的第二基板。 第一底面直接接触第二底面。 还提供了相关包和相关方法。

公开(公告)号：US20150155262A1

公开(公告)日：2015-06-04

申请号：US14617532

申请日：2015-02-09

Applicant: SK hynix Inc.

Inventor： Seung Jee KIM

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L24/83 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/295 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/13013 ,  H01L2224/131 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2224/83851 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/2064 ,  H01L2924/00

Abstract: The embedded package includes a semiconductor chip having contact portions disposed on a top surface thereof, a first dielectric layer substantially surrounding sidewalls of the semiconductor chip and including first fillers dispersed therein, a second dielectric layer substantially covering the top surface of the semiconductor chip and including second fillers dispersed therein, and first external interconnection portions disposed on the second dielectric layer and electrically connected to the contact portions, wherein an average size of the first fillers is different from that of the second fillers.

Abstract translation: 嵌入式封装包括具有设置在其顶表面上的接触部分的半导体芯片，基本上包围半导体芯片的侧壁并包括分散在其中的第一填料的第一电介质层，基本上覆盖半导体芯片的顶表面的第二电介质层， 第二填料分散在其中，第一外部互连部分设置在第二介电层上并电连接到接触部分，其中第一填料的平均尺寸不同于第二填料的平均尺寸。

公开(公告)号：US20150145121A1

公开(公告)日：2015-05-28

申请号：US14247023

申请日：2014-04-07

Applicant: SK HYNIX INC.

Inventor： Seung Jee KIM

IPC: H01L27/06 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/13 ,  H01L24/06 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06155 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An embedded package includes a core layer having a cavity, a first semiconductor chip disposed in the cavity, and bumps disposed on a top surface of the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the core layer, pads disposed on a top surface of the second semiconductor chip, and a first insulation layer disposed on the core layer and the first and second semiconductor chips. The first insulation layer has first openings that expose the bumps and second openings that expose the pads, and the first and second openings have a similar depth.

Abstract translation: 嵌入式封装包括具有空腔的芯层，设置在空腔中的第一半导体芯片和设置在第一半导体芯片的顶表面上的凸块，设置在第一半导体芯片和芯层上的第二半导体芯片， 在第二半导体芯片的顶表面上，以及设置在芯层和第一和第二半导体芯片上的第一绝缘层。 第一绝缘层具有暴露凸起的第一开口和露出垫的第二开口，并且第一和第二开口具有类似的深度。

公开(公告)号：US20150056755A1

公开(公告)日：2015-02-26

申请号：US14532393

申请日：2014-11-04

Applicant: SK hynix Inc.

Inventor： Seung Jee KIM ,  Qwan Ho CHUNG ,  Jong Hyun NAM ,  Si Han KIM ,  Sang Yong LEE ,  Seong Cheol SHIN

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/83 ,  H01L2224/02333 ,  H01L2224/02351 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03334 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/03474 ,  H01L2224/03903 ,  H01L2224/03906 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05017 ,  H01L2224/05026 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11602 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.

Abstract translation: 电子器件封装包括具有设置在半导体芯片的接触部分上的柱和从柱的上部侧向突出的扩大部分的凸块; 互连部分，其具有基本上围绕所述柱的扩大部分和上侧壁的锁定部分; 以及基本上围绕所述凸起和所述锁定部分的绝缘层，以将所述互连部分与所述半导体芯片分离。

公开(公告)号：US20140167276A1

公开(公告)日：2014-06-19

申请号：US13846829

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Seung Jee KIM

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L23/16 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/3512 ,  H01L2224/82 ,  H01L2224/83

Abstract: A semiconductor package includes a package substrate, semiconductor chips adhered over the package substrate and configured to include bonding pads, one or more dummy patterns disposed at specific intervals in peripheries of the semiconductor chips, an insulating layer formed over the package substrate including the semiconductor chips and the dummy patterns so that the bonding pads are exposed, and wire patterns formed over the insulating layer and coupled with the bonding pads.

Abstract translation: 半导体封装包括封装基板，粘附在封装基板上的半导体芯片，并且被配置为包括接合焊盘，在半导体芯片的周边以特定间隔设置的一个或多个虚设图案，形成在包括半导体芯片的封装基板上的绝缘层 以及虚设图案，使得接合焊盘露出，以及在绝缘层上形成并与接合焊盘耦合的导线图案。

公开(公告)号：US20140367851A1

公开(公告)日：2014-12-18

申请号：US14085357

申请日：2013-11-20

Applicant: SK HYNIX INC.

Inventor： Sang Yong LEE ,  Qwan Ho CHUNG ,  Seung Jee KIM ,  Jong Hyun NAM ,  Si Han KIM

IPC: H01L23/00

CPC classification number: H01L24/25 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embedded packages are provided. The embedded package includes a chip attached to a first surface of a core layer, a plurality of bumps on a surface of the chip opposite to the core layer, and a first insulation layer surrounding the core layer, the chip and the plurality of bumps. The first insulation layer has a trench disposed in a portion of the first insulation layer to expose the plurality of bumps.

Abstract translation: 提供嵌入式软件包。 嵌入式封装包括附着到芯层的第一表面的芯片，与芯层相对的芯片表面上的多个凸起，以及围绕芯层，芯片和多个凸块的第一绝缘层。 第一绝缘层具有设置在第一绝缘层的一部分中以暴露多个凸块的沟槽。

公开(公告)号：US20130147060A1

公开(公告)日：2013-06-13

申请号：US13756831

申请日：2013-02-01

Applicant: SK HYNIX INC.

Inventor： Jae Myun KIM ,  Seung Jee KIM ,  Ki Bum KIM

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes and extend laterally in opposite directions so as to define a zigzag arrangement together.

Abstract translation: 半导体封装包括衬底，附着到衬底的第一半导体芯片模块，附接到第一半导体芯片模块的导电连接构件和附接到导电连接构件的第二半导体芯片模块。 第一和第二半导体芯片模块形成为具有阶梯状形状并且沿相反方向横向延伸，以便将Z字形布置在一起。

公开(公告)号：US20150287702A1

公开(公告)日：2015-10-08

申请号：US14468885

申请日：2014-08-26

Applicant: SK hynix Inc.

Inventor： Seung Jee KIM ,  Qwan Ho CHUNG

IPC: H01L25/11 ,  H01L23/498

CPC classification number: H01L25/117 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/73267

Abstract: A package stacked device may include a first packaging body layer having a first chip embedded therein, and a second packaging body layer positioned under the first packaging body layer and having a second chip embedded therein. The package stacked device may also include a first connection unit protruding from a first bottom surface of the first packaging body layer, a second connection unit protruding from a second top surface of the second packaging body layer, a first covering layer providing a first opening to expose the top surface of the second connection unit and substantially covering the second top surface of the second packaging body layer, and a first adhesive layer substantially covering the exposed top surface of the second connection unit within the first opening. The first connection unit may be inserted into the first opening and connected to the first adhesive layer.

Abstract translation: 封装堆叠器件可以包括其中嵌入有第一芯片的第一封装体层和位于第一封装体层之下并具有嵌入其中的第二芯片的第二封装体层。 包装堆叠装置还可以包括从第一包装体层的第一底表面突出的第一连接单元，从第二包装体层的第二顶表面突出的第二连接单元，第一覆盖层， 暴露第二连接单元的顶表面并且基本上覆盖第二包装体层的第二顶表面，以及基本覆盖第一开口内的第二连接单元的暴露的顶表面的第一粘合剂层。 第一连接单元可插入第一开口并连接到第一粘合剂层。

公开(公告)号：US20150255427A1

公开(公告)日：2015-09-10

申请号：US14452323

申请日：2014-08-05

Applicant: SK HYNIX INC.

Inventor： Ki Jun SUNG ,  Seung Jee KIM ,  Jong Hyun NAM ,  Sang Yong LEE ,  Young Geun YOO

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/24 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15156 ,  H01L2924/3511

Abstract: A chip stack embedded package includes a first dielectric layer having a multistep cavity therein, a first plurality of semiconductor chips disposed in a first level of the multistep cavity, a second plurality of semiconductor chips disposed in a second level of the multistep cavity, and a second dielectric layer filling the multistep cavity to cover the first and second pluralities of semiconductor chips.

Abstract translation: 芯片堆叠嵌入式封装包括其中具有多级空腔的第一介电层，设置在多级腔的第一级中的第一多个半导体芯片，设置在多级腔的第二级中的第二多个半导体芯片，以及 填充多阶空腔以覆盖第一和第二多个半导体芯片的第二介电层。

公开(公告)号：US20150179608A1

公开(公告)日：2015-06-25

申请号：US14273485

申请日：2014-05-08

Applicant: SK HYNIX INC.

Inventor： Ki Jun SUNG ,  Seung Jee KIM ,  Jong Hyun NAM ,  Sang Yong LEE ,  Young Geun YOO

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/09134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/06541 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01029

Abstract: An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided.

Abstract translation: 嵌入式封装包括嵌入在封装衬底中的第一半导体芯片，设置在封装衬底的第一表面上的第二半导体芯片和设置在封装衬底的第一表面上以及位于封装衬底的侧壁之间的一组外部连接接头 第二半导体芯片和嵌入式封装的边缘。 还提供了相关的存储卡和相关的电子系统。