公开(公告)号：US20170170127A1

公开(公告)日：2017-06-15

申请号：US15243296

申请日：2016-08-22

Applicant: SK hynix Inc.

Inventor： Hyeong Seok CHOI ,  Ki Jun SUNG ,  Jong Hoon KIM ,  Young Geun YOO ,  Pil Soon BAE

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/552 ,  H01L23/562 ,  H01L24/14 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/83

Abstract: According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. A second dielectric layer may be formed to cover the redistribution lines. Related wafer level packages may also be provided.

公开(公告)号：US20170221868A1

公开(公告)日：2017-08-03

申请号：US15487078

申请日：2017-04-13

Applicant: SK hynix Inc.

Inventor： Jong Hoon KIM ,  Ki Jun SUNG ,  Young Geun YOO ,  Hyeong Seok CHOI

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/31058 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2924/00012

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

公开(公告)号：US20160247781A1

公开(公告)日：2016-08-25

申请号：US14811368

申请日：2015-07-28

Applicant: SK hynix Inc.

Inventor： Ki Jun SUNG ,  Young Geun YOO

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/29

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/065 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/92144 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321

Abstract: Semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom portion of the cavity. The semiconductor package may include a semiconductor chip disposed in the cavity and coupled to chip connectors, the chip connectors of the semiconductor chip inserted into the connection window. The semiconductor package may include a dielectric layer filling the cavity and the connection window and configured to expose end portions of the chip connectors and to substantially cover the semiconductor chip. Related memory cards and related electronic systems are also provided.

Abstract translation: 提供半导体封装。 半导体封装可以包括在其中包括空腔的嵌入衬底和在空腔的底部中的连接窗口。 半导体封装可以包括设置在空腔中并耦合到芯片连接器的半导体芯片，半导体芯片的芯片连接器插入连接窗口中。 半导体封装可以包括填充空腔和连接窗口并被配置为暴露芯片连接器的端部并且基本上覆盖半导体芯片的电介质层。 还提供了相关的存储卡和相关的电子系统。

公开(公告)号：US20150255427A1

公开(公告)日：2015-09-10

申请号：US14452323

申请日：2014-08-05

Applicant: SK HYNIX INC.

Inventor： Ki Jun SUNG ,  Seung Jee KIM ,  Jong Hyun NAM ,  Sang Yong LEE ,  Young Geun YOO

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/24 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15156 ,  H01L2924/3511

Abstract: A chip stack embedded package includes a first dielectric layer having a multistep cavity therein, a first plurality of semiconductor chips disposed in a first level of the multistep cavity, a second plurality of semiconductor chips disposed in a second level of the multistep cavity, and a second dielectric layer filling the multistep cavity to cover the first and second pluralities of semiconductor chips.

Abstract translation: 芯片堆叠嵌入式封装包括其中具有多级空腔的第一介电层，设置在多级腔的第一级中的第一多个半导体芯片，设置在多级腔的第二级中的第二多个半导体芯片，以及 填充多阶空腔以覆盖第一和第二多个半导体芯片的第二介电层。

公开(公告)号：US20150179608A1

公开(公告)日：2015-06-25

申请号：US14273485

申请日：2014-05-08

Applicant: SK HYNIX INC.

Inventor： Ki Jun SUNG ,  Seung Jee KIM ,  Jong Hyun NAM ,  Sang Yong LEE ,  Young Geun YOO

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/09134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/06541 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01029

Abstract: An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided.

Abstract translation: 嵌入式封装包括嵌入在封装衬底中的第一半导体芯片，设置在封装衬底的第一表面上的第二半导体芯片和设置在封装衬底的第一表面上以及位于封装衬底的侧壁之间的一组外部连接接头 第二半导体芯片和嵌入式封装的边缘。 还提供了相关的存储卡和相关的电子系统。