公开(公告)号：US20240292676A1

公开(公告)日：2024-08-29

申请号：US18574429

申请日：2021-08-18

Applicant: Sharp Display Technology Corporation

Inventor： Tadayoshi MIYAMOTO ,  Yoshinobu NAKAMURA ,  Toshihiro KANEKO

IPC: H10K59/124 ,  H10K59/12

CPC classification number: H10K59/124 ,  H10K59/1201

Abstract: A first TFT includes: a first semiconductor layer of a polysilicon; and a first gate electrode on the first semiconductor layer via a first gate insulating film. A second TFT includes: a first conductive layer and a second conductive layer made of the same material, and provided in the same layer, as the first semiconductor layer; a second semiconductor layer of an oxide semiconductor on the first conductive layer and the second conductive layer; and a second gate electrode on the second semiconductor layer via the second gate insulating film.

公开(公告)号：US20250133829A1

公开(公告)日：2025-04-24

申请号：US18902923

申请日：2024-10-01

Applicant: Sharp Display Technology Corporation

Inventor： Toshihiro KANEKO ,  Yoshinobu Nakamura ,  Tadayoshi Miyamoto

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368

Abstract: An array substrate includes: a semiconductor film disposed on an upper-layer side of an insulating substrate; a gate insulating film disposed in a layer above the semiconductor film; a gate electrode disposed in a layer above the gate insulating film; an interlayer insulating film disposed in a layer above the gate electrode; a thin film transistor including a source electrode and a drain electrode disposed on the upper-layer side of the gate electrode via the interlayer insulating film; and a gate wiring line continuously formed with the gate electrode of the thin film transistor, wherein the gate electrode and the gate wiring line include an aluminum film, and a protective metal film made of a metal material having a melting point higher than a melting point of aluminum, and covering an entire surface of the aluminum film.

公开(公告)号：US20230244114A1

公开(公告)日：2023-08-03

申请号：US18095821

申请日：2023-01-11

Applicant: Sharp Display Technology Corporation

Inventor： Tadayoshi MIYAMOTO ,  Yoshitaka KOYAMA ,  Yoshinobu NAKAMURA ,  Toshihiro KANEKO

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124

Abstract: An active matrix substrate includes, in each pixel region, a pixel TFT of an oxide semiconductor layer having source and drain regions, a first insulating layer disposed on top of the oxide semiconductor layer, an extraction electrode, disposed on top of the first insulating layer, that includes a transparent conductive film, and a pixel electrode connected to the extraction electrode. The first insulating layer includes first and second contact holes located above the source and drain regions, respectively. Part of a source bus line overlaps part of the source region and is connected to the source region via the first contact hole. The extraction electrode is connected to the drain region via the second contact hole. Shapes of bottoms of the first and second contact holes are different from each other, and the shape of the bottom of the second contact hole includes two orthogonal sides.

公开(公告)号：US20250127015A1

公开(公告)日：2025-04-17

申请号：US18686488

申请日：2021-10-25

Applicant: Sharp Display Technology Corporation

Inventor： Toshihiro KANEKO

IPC: H10K59/80 ,  H10K59/131

Abstract: Each lead wiring line includes a first wiring line provided on a display region side and formed of the same material and in the same layer as a second metal layer, a second wiring line provided on a bending portion side and formed of the same material and in the same layer as the second metal layer, and a third wiring line provided between the first wiring line and the second wiring line, formed of the same material and in the same layer as the first metal layer and electrically connected to each of the first wiring line and the second wiring line via a first contact hole and a second contact hole formed in an inorganic insulating film.

公开(公告)号：US20250116906A1

公开(公告)日：2025-04-10

申请号：US18883192

申请日：2024-09-12

Applicant: Sharp Display Technology Corporation

Inventor： Tadayoshi MIYAMOTO ,  Yoshinobu NAKAMURA ,  Toshihiro KANEKO ,  Sohtaroh TANAKA

IPC: G02F1/1368 ,  G02F1/1333 ,  H01L27/12 ,  H01L29/786

Abstract: A transistor includes a semiconductor portion extending in a first direction, a first electrode extending in a second direction intersecting the first direction and is disposed overlapping a portion of the semiconductor portion, a first insulating film that is interposed between the first electrode and the semiconductor portion, a second electrode that is connected to the semiconductor portion, and a third electrode that is connected to the semiconductor portion, in which the first insulating film includes a first thick portion and a second thick portion having a film thickness greater than that of the first thick portion, at least two of the first thick portions are disposed at intervals in the second direction at positions overlapping both the first electrode and the semiconductor portion, and the second thick portion is disposed to be interposed between the two first thick portions in the second direction at a position overlapping both the first electrode and the semiconductor portion.