公开(公告)号：US20030107124A1

公开(公告)日：2003-06-12

申请号：US10211430

申请日：2002-08-02

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Chien-Ping Huang

IPC: H01L023/10

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package with a heat dissipating structure is provided. The heat dissipating structure includes a flat portion, and a plurality of support portions formed at edge comers of the flat portion for supporting the flat portion above a chip mounted on a substrate. The support portions are mounted at predetermined area on the substrate without interfering with arrangement of the chip and bonding wires that electrically connect the chip to the substrate. The support portions are arranged to form a space embraced by adjacent supports and the flat portion, so as to allow the bonding wires to pass through the space to reach area on the substrate outside coverage of the heat dissipating structure; besides, passive components or other electronic components can be mounted on the substrate at area within or outside the coverage of the heat dissipating structure, thereby improving flexibility in component arrangement in the semiconductor package.

Abstract translation: 提供具有散热结构的半导体封装。 散热结构包括平坦部分和形成在平坦部分的边缘角处的多个支撑部分，用于将平坦部分支撑在安装在基板上的芯片上。 支撑部分安装在基板上的预定区域上，而不干扰将芯片与基板电连接的芯片和接合线的布置。 支撑部分被布置成形成由相邻支撑件和平坦部分包围的空间，以便使接合线通过该空间以到达散热结构外部覆盖层上的基板上的区域; 此外，无源部件或其他电子部件可以在散热结构的覆盖范围内或外部的区域处安装在基板上，从而提高半导体封装中的部件布置的灵活性。

公开(公告)号：US20030089983A1

公开(公告)日：2003-05-15

申请号：US10039884

申请日：2002-01-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Eric Ko ,  Chih-Ming Huang

IPC: H01L023/48

CPC classification number: H01L24/85 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8485 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.

Abstract translation: 提出了一种球栅阵列半导体封装，其中至少芯片安装在基板上，并且芯片上的信号焊盘通过接合线与基板上的信号指状电连接。 功率板和接地板的两端各自分别连接到芯片和基板上的预定位置，而不会妨碍接合线。 在基板上不必形成功率环或接地环，从而减少对基板的微量可路由性的限制。 此外，由于不设置电源线或接地线，因此不太可能发生接合线的短路，从而提高了生产率。 此外，功率板和接地板提供屏蔽效果，用于保护芯片免受外部电磁干扰，并且部分地与大气直接接触，以提高半导体封装的散热效率。

公开(公告)号：US20020195717A1

公开(公告)日：2002-12-26

申请号：US10219245

申请日：2002-08-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: B82Y15/00 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A stacked dual-chip semiconductor packaging technology is proposed for the packaging of two semiconductor chips in one single package unit. The proposed dual-chip semiconductor package is characterized by an intercrossedly-stacked dual-chip arrangement which is constructed on a specially-designed leadframe having a supporting frame; a die pad supported on the supporting frame and having a peripherally-located upper portion and a centrally-located downset portion; and a set of leads linked to the supporting frame and arranged around the die pad. By the proposed packaging technology, a first semiconductor chip is mounted within the downset portion of the die pad, while a second semiconductor chip is mounted on the upper portion of the die pad in an intercrossedly-stacked manner in relation to the first semiconductor chip. Compared to the prior art, the proposed technology allows the packaging process to be implemented in a less complex and more cost-effective manner. Moreover, since the underlying chip is attached to die pad, it allows an increased heat-dissipation efficiency to the semiconductor package.

Abstract translation: 提出了一种堆叠的双芯片半导体封装技术，用于在一个封装单元中封装两个半导体芯片。 所提出的双芯片半导体封装的特征在于跨交叠堆叠的双芯片布置，其构造在具有支撑框架的特殊设计的引线框架上; 支撑在所述支撑框架上并且具有外围定位的上部和位于中心的下降部分的管芯焊盘; 以及连接到支撑框架并且布置在管芯焊盘周围的一组引线。 通过提出的封装技术，将第一半导体芯片安装在芯片焊盘的压缩部分内，而第二半导体芯片相对于第一半导体芯片以交叉交叠的方式安装在芯片焊盘的上部。 与现有技术相比，所提出的技术允许以不那么复杂和更具成本效益的方式实现包装过程。 此外，由于底层芯片附接到管芯焊盘，因此允许对半导体封装件的散热效率提高。

公开(公告)号：US20020175401A1

公开(公告)日：2002-11-28

申请号：US09922270

申请日：2001-08-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Tzong-Da Ho ,  Cheng-Hsu Hsiao

IPC: H01L023/02 ,  H01L023/34 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L23/4334 ,  H01L23/16 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package with stacked chips is proposed, in which a first chip mounted on and electrically connected to a chip carrier is attached with a rigid interposer thereto, while the rigid interposer has a second chip disposed thereon in a manner that the rigid interposer is interposed between the first chip and the second chip. With the use of the rigid interposer, the second chip stacked on the first chip can be positioned in planarily parallel to the chip carrier, allowing bonding wires for electrically connecting the second chip to the chip carrier to be bonded completely. Moreover, the second chip has portions thereof not located right above the first chip to be firmly supported by the rigid interposer, and thus the second chip can be prevented from cracking in the wire bonding process. Furthermore, on the chip carrier there is formed an encapsulant for encapsulating the first chip, the second chip and part of the chip carrier where the first and second chips are electrically connected thereto,

Abstract translation: 提出了一种具有堆叠芯片的半导体封装，其中安装在芯片载体上并电连接到芯片载体的第一芯片附有刚性插入件，而刚性插入件具有设置在其上的第二芯片，其中刚性插入件插入 在第一芯片和第二芯片之间。 通过使用刚性插入件，堆叠在第一芯片上的第二芯片可以平行地平行于芯片载体定位，从而允许用于将第二芯片电连接到芯片载体的接合线完全粘合。 此外，第二芯片的部分不位于第一芯片的正上方，以由刚性插入件牢固地支撑，因此可以防止第二芯片在引线接合过程中破裂。 此外，在芯片载体上形成用于封装第一芯片，第二芯片和芯片载体的一部分的密封剂，其中第一芯片和第二芯片与其电连接，

公开(公告)号：US20020093091A1

公开(公告)日：2002-07-18

申请号：US09838521

申请日：2001-04-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Zong-Da Ho ,  Che-Jung Chang

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L023/34 ,  H01L023/52

CPC classification number: H05K1/116 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/11 ,  H01L2924/14 ,  H05K1/112 ,  H05K3/3478 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/09663 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/1178 ,  H01L2924/00

Abstract: A method for fabricating a ground-ball bonding structure on a TBGA package is proposed, which is characterized by the forming of a plurality of air vents around the ground-ball pad and cut all the way into the tape until reaching the bottommost surface of the tape. During solder-reflow process, this allows the trapped air in the via hole due to solder material being filled into the via hole to the outside atmosphere during solder-reflow process. Compared to the prior art, since the proposed method allows substantially no air-filled voids to be left in the via hole, the resulted ground ball would be fully collapsed against the heat sink and therefore coplanarized with respect to the signal ball. The coplanarity of the overall ball grid array would allow the TBGA package to be mounted properly onto a printed circuit board during SMT (Surface Mount Technology) process. In addition, the proposed method allows a reliable bonding between the ground ball and the heat sink thus assuring the grounding effect of the resulted TBGA package.

Abstract translation: 提出了一种在TBGA封装上制造地球接合结构的方法，其特征在于在地球垫周围形成多个通风孔，并将其全部切入带中，直至达到 胶带。 在焊锡回流工艺期间，由于在焊料回流过程中由于焊料材料被填充到通孔中而导致通孔中的被捕获的空气进入外部大气。 与现有技术相比，由于所提出的方法基本上没有空气填充的空隙留在通孔中，因此所产生的磨球将完全折叠在散热片上，因此相对于信号球共面。 整个球栅阵列的共面性将允许在SMT（表面贴装技术）工艺中将TBGA封装适当地安装到印刷电路板上。 此外，所提出的方法允许接地球和散热器之间的可靠接合，从而确保所得TBGA封装的接地效果。

公开(公告)号：US20020033527A1

公开(公告)日：2002-03-21

申请号：US09908191

申请日：2001-07-18

Applicant: Siliconware precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Jui-Meng Jao

IPC: H01L023/22

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device and a manufacturing process thereof are proposed. With no use of a substrate or leads, the foregoing semiconductor device has a chip with its surfaces being exposed to the outside of the device, allowing the overall thickness of the device to be significantly minimized, and the heat-dissipating efficiency to be greatly improved, as well as the manufacturing process and cost to be simplified and reduced respectively. Moreover, unlike a conventional semiconductor device, the semiconductor device is manufactured without using a specific mold with protrusions, a drill or a laser beam, so that the manufacturing cost is further reduced, and crack in the encapsulant as well as flash during molding are prevented.

Abstract translation: 提出了一种半导体器件及其制造方法。 在不使用基板或引线的情况下，上述半导体器件具有将其表面暴露于器件外部的芯片，从而能够使器件的整体厚度显着降低，从而大大提高散热效率 ，以及分别简化和减少的制造工艺和成本。 此外，与传统的半导体器件不同，在不使用具有突起，钻头或激光束的特定模具的情况下制造半导体器件，从而进一步降低制造成本，并且防止密封剂中的裂纹以及模制期间的闪光。 。

公开(公告)号：US20040251538A1

公开(公告)日：2004-12-16

申请号：US10690921

申请日：2003-10-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Han-Ping Pu ,  Chien-Ping Huang

IPC: H01L023/34

CPC classification number: H01L23/367 ,  H01L23/3672 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2224/05599

Abstract: A semiconductor package with a heat sink is provided. At least one chip and a heat sink attached to the chip are mounted on a substrate. At least one slot is formed through at least one corner of the heat sink at a position attached to the substrate. An adhesive material is applied between the heat sink and substrate and over filled in the slot with an overflow of the adhesive material out of the slot. The adhesive material over filled in the slot provides an anchoring effect and increases its contact area with the heat sink to thereby firmly secure the heat sink on the substrate. Further, the slot formed at the corner of the heat sink can alleviate thermal stresses accumulated at the corner of the heat sink and thereby prevent delamination between the heat sink and the substrate.

Abstract translation: 提供了具有散热器的半导体封装。 连接到芯片的至少一个芯片和散热片安装在基板上。 在连接到基板的位置处，通过散热器的至少一个角部形成至少一个槽。 将粘合剂材料施加在散热器和衬底之间并且在填充在槽中并且粘合剂材料溢出出槽之外。 填充在槽中的粘合剂材料提供锚定效果并增加其与散热器的接触面积，从而将散热器牢固地固定在基板上。 此外，形成在散热器角落处的槽可以减轻积聚在散热器拐角处的热应力，从而防止散热器和基板之间的分层。

公开(公告)号：US20040245608A1

公开(公告)日：2004-12-09

申请号：US10643375

申请日：2003-08-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC: H01L023/495

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor package having conductive bumps on a chip and a fabrication method thereof are provided. A plurality of the conductive bumps are deposited respectively on bond pads of the chip. An encapsulation body encapsulates the chip and conductive bumps while exposing ends of the conductive bumps. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the exposed ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings for exposing predetermined portions of the conductive traces. The exposed portions of the conductive traces are connected to a plurality of solder balls respectively. The conductive bumps on the bond pads of the chip allow easy positional recognition of the bond pads, making the conductive traces well electrically connected to the bond pads through the conductive bumps and assuring the quality and reliability of the semiconductor package.

Abstract translation: 提供了一种在芯片上具有导电凸块的半导体封装及其制造方法。 多个导电凸块分别沉积在芯片的接合焊盘上。 封装体封装芯片和导电凸块，同时暴露导电凸块的端部。 多个导电迹线形成在封装主体上并与导电凸块的暴露端电连接。 焊接掩模层施加在导电迹线上并形成有用于暴露导电迹线的预定部分的开口。 导电迹线的暴露部分分别连接到多个焊球。 芯片的接合焊盘上的导电凸块允许接合焊盘的容易的位置识别，使得导电迹线通过导电凸块良好地电连接到接合焊盘，并确保半导体封装的质量和可靠性。

公开(公告)号：US20040183174A1

公开(公告)日：2004-09-23

申请号：US10768307

申请日：2004-01-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang ,  Chih-Ming Huang

IPC: H01L023/02

CPC classification number: H01L23/552 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49568 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Abstract translation: 提出了具有增强的电气和热性能的BGA（球栅阵列）封装以及制造BGA封装的方法。 该BGA封装的特征在于使用功率连接散热器和接地连接散热器，其分别用于将电源焊盘和接地焊盘电连接到封装芯片，以及散发由芯片产生的热量 操作。 地面连接散热器布置成完全覆盖芯片，从而为芯片提供良好的屏蔽效果，有助于提高芯片在运行过程中的电气性能。 此外，地连接散热器部分地暴露于封装芯片的封装体的外部，由此可以实现令人满意的散热效率。

公开(公告)号：US20030214048A1

公开(公告)日：2003-11-20

申请号：US10456251

申请日：2003-06-05

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Chuan Wu ,  Chien-Ping Huang

IPC: H01L023/48

CPC classification number: H01L24/33 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding portion. A wire bonding region and a bump attach region are respectively defined on opposite surfaces of the protruding portion, and staggered in position. This allows a force applied from a wire bonder to the wire bonding regions not to adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions spaced apart from the bump attach regions can be prevented from being contaminated by an etching solution used in solder bump implantation, so that wire bonding quality can be well maintained.

Abstract translation: 提出了一种QFN半导体封装及其制造方法，其中采用具有多个引线的引线框架，并且每个引线的内端形成有突出部分。 引线接合区域和突起附着区域分别限定在突出部分的相对表面上并且交错位置。 这允许从引线接合器施加到引线接合区域的力不会不利地影响注入在凸块附接区域上的焊料凸起，使得焊料凸块可以在结构上确保而不会破裂。 此外，可以防止与凸块附接区域间隔开的引线接合区域被焊料凸块注入中使用的蚀刻溶液污染，从而可以良好地保持引线接合质量。