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    MEMORY DEVICE
    1.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20200302989A1

    公开(公告)日：2020-09-24

    申请号：US16566396

    申请日：2019-09-10

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yoshiaki OSADA ,  Kosuke HATSUDA

    IPC: G11C11/16

    Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.

    MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20180277188A1

    公开(公告)日：2018-09-27

    申请号：US15703456

    申请日：2017-09-13

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yorinobu FUJINO ,  Kosuke HATSUDA ,  Yoshiaki OSADA

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1655

    Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.

    SEMICONDUCTOR STORAGE DEVICE
    5.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20190287594A1

    公开(公告)日：2019-09-19

    申请号：US16124007

    申请日：2018-09-06

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yoshiaki OSADA ,  Kosuke HATSUDA

    IPC: G11C11/16 ,  H01L27/22 ,  H01F10/32 ,  H01L43/02

    Abstract: According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190088303A1

    公开(公告)日：2019-03-21

    申请号：US15917377

    申请日：2018-03-09

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Fumiyoshi MATSUOKA ,  Kosuke HATSUDA

    IPC: G11C11/16

    Abstract: According to one embodiment, a semiconductor memory device comprises a first memory cell including a first resistance change element; and a write circuit configured to write data to the first memory cell. The write circuit includes a first circuit including a first input terminal supplied with a first signal based on read data from the first memory cell and a second input terminal supplied with a second signal based on write data to the first memory cell; and a second circuit including a first input terminal supplied with a third signal from an output terminal of the first circuit and a second input terminal supplied with a fourth signal.

    MEMORY SYSTEM STORING MANAGEMENT INFORMATION AND METHOD OF CONTROLLING SAME
    8.
    发明申请
    MEMORY SYSTEM STORING MANAGEMENT INFORMATION AND METHOD OF CONTROLLING SAME 有权

    公开(公告)号：US20210232326A1

    公开(公告)日：2021-07-29

    申请号：US17229096

    申请日：2021-04-13

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Junji YANO ,  Hidenori MATSUZAKI ,  Kosuke HATSUDA

    IPC: G06F3/06 ,  G06F11/14 ,  G11C7/20 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G06F12/02

    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

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