公开(公告)号：US20190088298A1

公开(公告)日：2019-03-21

申请号：US15918399

申请日：2018-03-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kosuke HATSUDA ,  Yoshiaki OSADA ,  Yorinobu FUJINO ,  Jieyun ZHOU

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0057 ,  H01F10/3254 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.

公开(公告)号：US20190287594A1

公开(公告)日：2019-09-19

申请号：US16124007

申请日：2018-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki OSADA ,  Kosuke HATSUDA

IPC: G11C11/16 ,  H01L27/22 ,  H01F10/32 ,  H01L43/02

Abstract: According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.

公开(公告)号：US20200302989A1

公开(公告)日：2020-09-24

申请号：US16566396

申请日：2019-09-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki OSADA ,  Kosuke HATSUDA

IPC: G11C11/16

Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.

公开(公告)号：US20180277188A1

公开(公告)日：2018-09-27

申请号：US15703456

申请日：2017-09-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yorinobu FUJINO ,  Kosuke HATSUDA ,  Yoshiaki OSADA

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1655

Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.

公开(公告)号：US20180012640A1

公开(公告)日：2018-01-11

申请号：US15694587

申请日：2017-09-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki OSADA ,  Kosuke HATSUDA

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08

CPC classification number: G11C11/1673 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1697 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2013/0054 ,  H01L27/228 ,  H01L43/08

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.

公开(公告)号：US20180074737A1

公开(公告)日：2018-03-15

申请号：US15457518

申请日：2017-03-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki OSADA ,  Katsuhiko HOYA ,  Yorinobu FUJINO ,  Kosuke HATSUDA

IPC: G06F3/06 ,  G11C11/16 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/52 ,  G11C29/781

Abstract: According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.

公开(公告)号：US20170364407A1

公开(公告)日：2017-12-21

申请号：US15692971

申请日：2017-08-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki OSADA ,  Katsuhiko HOYA

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/106 ,  G06F11/3037 ,  G06F2201/81 ,  G06F2201/88 ,  G11C17/16 ,  G11C17/18 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: According to one embodiment, a memory system includes: a first memory cell area where a first memory cell is provided; a second memory cell area where a second memory cell is provided; an ECC circuit which corrects an error of data stored by the first memory cell; and a control circuit which replaces the first memory cell with the second memory cell if the number of times an error is successfully corrected in the first memory cell reaches a first value.