公开(公告)号：US20160284627A1

公开(公告)日：2016-09-29

申请号：US15174983

申请日：2016-06-06

Applicant: Tessera, Inc.

Inventor： Vage OGANESIAN ,  Belgacem HABA ,  Ilyas MOHAMMED ,  Craig MITCHELL ,  Piyush SAVALIA

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.

公开(公告)号：US20140319699A1

公开(公告)日：2014-10-30

申请号：US14329744

申请日：2014-07-11

Applicant: Tessera, Inc.

Inventor： Cyprian Emeka UZOH ,  Belgacem HABA ,  Craig MITCHELL

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

公开(公告)号：US20170098621A1

公开(公告)日：2017-04-06

申请号：US15379895

申请日：2016-12-15

Applicant: Tessera, Inc.

Inventor： Cyprian UZOH ,  Vage OGANESIAN ,  Ilyas MOHAMMED ,  Belgacem HABA ,  Piyush SAVALIA ,  Craig MITCHELL

IPC: H01L23/00 ,  H05K3/40 ,  H05K1/09

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/056 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/013 ,  H05K1/09 ,  H05K3/4007 ,  H05K2201/032 ,  H05K2201/0326 ,  H05K2201/0338

Abstract: An electrical connection structure includes a variable-composition nickel alloy layer with a minor constituent selected from a group consisting of boron, carbon, and tungsten, wherein at least over a portion of a conductive substrate, the concentration of the minor constituent varies throughout the variable-composition nickel alloy layer in a direction from the bottom surface of the variable-composition nickel alloy layer to the top surface of the variable-composition nickel alloy layer.

公开(公告)号：US20180130746A1

公开(公告)日：2018-05-10

申请号：US15823210

申请日：2017-11-27

Applicant: Tessera, Inc.

Inventor： Vage OGANESIAN ,  Ilyas MOHAMMED ,  Craig MITCHELL ,  Belgacem HABA ,  Piyush SAVALIA

IPC: H01L23/538 ,  H01L23/00 ,  H01L27/146 ,  H01L23/31 ,  H01L25/065 ,  H01L29/06 ,  H01L25/00 ,  H01L23/48

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L29/0657 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

公开(公告)号：US20170294376A1

公开(公告)日：2017-10-12

申请号：US15623228

申请日：2017-06-14

Applicant: Tessera, Inc.

Inventor： Cyprian Emeka UZOH ,  Belgacem HABA ,  Craig MITCHELL

IPC: H01L23/528 ,  H01L21/321 ,  H01L23/522 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

公开(公告)号：US20150279730A1

公开(公告)日：2015-10-01

申请号：US14731251

申请日：2015-06-04

Applicant: Tessera, Inc.

Inventor： Cyprian UZOH ,  Vage OGANESIAN ,  Ilyas MOHAMMED ,  Craig MITCHELL ,  Belgacem HABA

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

Abstract translation: 仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。 该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。 该方法可以包括在不同的去除条件下从多层结构去除材料。 还公开了具有不同尺寸的多个空腔的多层镶嵌结构。 空腔可以具有平滑的内壁表面。 结构的层可以直接接触。 空腔可以用导电金属或绝缘体填充。 进一步公开了使用这些方法和结构的多层半导体器件。