公开(公告)号：US09653319B2

公开(公告)日：2017-05-16

申请号：US14532859

申请日：2014-11-04

Applicant: Tokyo Electron Limited

Inventor： Anton J. deVilliers ,  Kaushik Kumar

IPC: G03F7/26 ,  H01L21/311 ,  H01L21/027 ,  H01L21/033

CPC classification number: H01L21/31144 ,  G03F7/26 ,  G03F7/265 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31116

Abstract: Methods for using high-speed EUV resists including resists having additives that may be detrimental to etch chambers. Methods include using reversal materials and/or reversal techniques, as well as diffusion-limited etch-back and slimming for pattern creation and transfer. A substrate with high-speed EUV resist is lithographically patterned and developed into a patterned resist mask. An image reversal material is then over-coated on the patterned resist mask such that the image reversal material fills and covers the patterned resist mask. An upper portion of the image reversal material is removed such that top surfaces of the patterned resist mask are exposed. The patterned resist mask is removed such that the image reversal material remains resulting in a patterned image reversal material mask. Residual resist material is removed via a slimming process using an acid diffusion and subsequent development.

公开(公告)号：US20150132965A1

公开(公告)日：2015-05-14

申请号：US14532859

申请日：2014-11-04

Applicant: Tokyo Electron Limited

Inventor： Anton J. deVilliers ,  Kaushik Kumar

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/31144 ,  G03F7/26 ,  G03F7/265 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31116

Abstract: Methods for using high-speed EUV resists including resists having additives that may be detrimental to etch chambers. Methods include using reversal materials and/or reversal techniques, as well as diffusion-limited etch-back and slimming for pattern creation and transfer. A substrate with high-speed EUV resist is lithographically patterned and developed into a patterned resist mask. An image reversal material is then over-coated on the patterned resist mask such that the image reversal material fills and covers the patterned resist mask. An upper portion of the image reversal material is removed such that top surfaces of the patterned resist mask are exposed. The patterned resist mask is removed such that the image reversal material remains resulting in a patterned image reversal material mask. Residual resist material is removed via a slimming process using an acid diffusion and subsequent development.

Abstract translation: 使用高速EUV抗蚀剂的方法包括具有可能对腐蚀室有害的添加剂的抗蚀剂。 方法包括使用反向材料和/或反转技术，以及用于图案创建和转移的扩散限制的回蚀和减肥。 具有高速EUV抗蚀剂的衬底被光刻图案化并显影成图案化的抗蚀剂掩模。 然后将图像反转材料涂覆在图案化的抗蚀剂掩模上，使得图像反转材料填充并覆盖图案化的抗蚀剂掩模。 去除图像反转材料的上部，使得图案化抗蚀剂掩模的顶表面露出。 去除图案化的抗蚀剂掩模，使得图像反转材料保持得到图案化的图像反转材料掩模。 残余抗蚀剂材料通过使用酸扩散和随后显影的减肥方法除去。

公开(公告)号：US08945408B2

公开(公告)日：2015-02-03

申请号：US13918794

申请日：2013-06-14

Applicant: Tokyo Electron Limited

Inventor： Vidhya Chakrapani ,  Akiteru Ko ,  Kaushik Kumar

IPC: C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/311

CPC classification number: H01L21/31138 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0337 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/67248 ,  H01L22/12

Abstract: Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the surface of the substrate, the etching process being performed at a substrate temperature less than or equal to about 20 degrees C. The method further comprises providing a substrate holder for supporting the substrate, the substrate holder having a first temperature control element for controlling a first temperature at a central region and second temperature control element at an edge region of the substrate and setting a target value for the first and the second temperature.

Abstract translation: 提供了一种制备图案化定向自组装层的方法，包括：提供具有嵌段共聚物层的基材，所述嵌段共聚物层包含在嵌段共聚物层中限定第一图案的第一相分离聚合物和限定第二相分离聚合物的第二相分离聚合物 嵌段共聚物层中的图案; 并且执行蚀刻工艺以选择性地除去第二相分离聚合物，同时留下基材表面上的第一相分离聚合物的第一图案，蚀刻工艺在小于或等于约20的衬底温度下进行 该方法还包括提供用于支撑衬底的衬底保持器，衬底保持器具有用于控制中心区域的第一温度的第一温度控制元件和在衬底的边缘区域处的第二温度控制元件，并且设置靶 第一和第二温度的值。

公开(公告)号：US10600687B2

公开(公告)日：2020-03-24

申请号：US15491786

申请日：2017-04-19

Applicant: Tokyo Electron Limited

Inventor： Aelan Mosden ,  Kaushik Kumar

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L21/033 ,  H01L29/66

Abstract: Process integration techniques are disclosed that use a carbon fill layer during formation of self-aligned structures. A carbon layer may be placed over an etch stop layer. A cap layer may be provided over the carbon layer. The carbon layer may fill a high aspect ratio structure formed on the substrate. The carbon layer may be removed from a substrate in a highly selective removal technique in a manner that does not damage underlying layers. The carbon layer may fill a self-aligned contact region that is provided for a self-aligned contact process flow. A tone inversion mask may be used to protect multiple self-aligned contact regions. With the blocking mask in place, the carbon layer may be removed from regions that are not the self-aligned contact region. After removal of the blocking mask, the carbon layer which fills the self-aligned contacts may then be removed.

公开(公告)号：US20210313217A1

公开(公告)日：2021-10-07

申请号：US17223876

申请日：2021-04-06

Applicant: Tokyo Electron Limited ,  IMEC VZW

Inventor： Kaushik Kumar ,  Yannick Feurprier ,  Zsolt Tokei

IPC: H01L21/768

Abstract: In certain embodiments, a method includes forming a first etch stop layer on a first metallization layer of a semiconductor substrate. The method further includes forming, prior to forming a second metallization layer over the first metallization layer, an opening in the first etch stop layer according to a supervia mask. The method further includes forming the second metallization layer over the first metallization layer and forming a second etch stop layer on the second metallization layer. The method further includes forming, prior to forming a third metallization layer over the second metallization layer, an opening in the second etch stop layer according to the supervia mask. The method further includes forming the third metallization layer over the second metallization layer and etching a supervia opening from the third metallization layer to the first metallization layer according to the supervia mask.

公开(公告)号：US20180308753A1

公开(公告)日：2018-10-25

申请号：US15491786

申请日：2017-04-19

Applicant: Tokyo Electron Limited

Inventor： Aelan Mosden ,  Kaushik Kumar

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/28

Abstract: Process integration techniques are disclosed that use a carbon fill layer during formation of self-aligned structures. A carbon layer may be placed over an etch stop layer. A cap layer may be provided over the carbon layer. The carbon layer may fill a high aspect ratio structure formed on the substrate. The carbon layer may be removed from a substrate in a highly selective removal technique in a manner that does not damage underlying layers. The carbon layer may fill a self-aligned contact region that is provided for a self-aligned contact process flow. A tone inversion mask may be used to protect multiple self-aligned contact regions. With the blocking mask in place, the carbon layer may be removed from regions that are not the self-aligned contact region. After removal of the blocking mask, the carbon layer which fills the self-aligned contacts may then be removed.