公开(公告)号：US20210265205A1

公开(公告)日：2021-08-26

申请号：US17179117

申请日：2021-02-18

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Xinghua Sun ,  Michael Edley ,  Angelique Raley

IPC: H01L21/768

Abstract: Stacked structures, process steps, and methods for via and trench formation use a dielectric etch stop layer (ESL) to reduce or eliminate problems, such as process lag and chamfer erosion, that occur during conventional etch processes. A stacked structure is formed that includes a dielectric ESL within a dielectric layer, such as a low-dielectric (low-K) layer, to form a first low-K layer below the dielectric ESL and a second low-K dielectric layer above the dielectric ESL. When the stacked structure is subsequently etched to form trenches as well as vias through the stacked structure to underlying layers, the dielectric ESL reduces or eliminates RIE lag by ensuring that trenches (regardless of width) stop on the dielectric ESL. The dielectric ESL also acts as a protective layer to protect corners from chamfer erosion during via and trench etch processes.

公开(公告)号：US20220189764A1

公开(公告)日：2022-06-16

申请号：US17653252

申请日：2022-03-02

Applicant: Tokyo Electron Limited

Inventor： Michael Edley ,  Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  Henan Zhang ,  Hiroyuki Suzuki ,  Shan Hu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/67

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

公开(公告)号：US11289325B2

公开(公告)日：2022-03-29

申请号：US17180077

申请日：2021-02-19

Applicant: Tokyo Electron Limited

Inventor： Michael Edley ,  Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  Henan Zhang ,  Hiroyuki Suzuki ,  Shan Hu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/67

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

公开(公告)号：US20210407790A1

公开(公告)日：2021-12-30

申请号：US17180077

申请日：2021-02-19

Applicant: Tokyo Electron Limited

Inventor： Michael Edley ,  Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  Henan Zhang ,  Hiroyuki Suzuki ,  Shan Hu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/67

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.