公开(公告)号：US20240282597A1

公开(公告)日：2024-08-22

申请号：US18112120

申请日：2023-02-21

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Peter D'Elia

IPC: H01L21/67 ,  H01L21/02 ,  H01L21/687

CPC classification number: H01L21/67051 ,  H01L21/02052 ,  H01L21/67034 ,  H01L21/68764

Abstract: Improved puddle processes and methods are provided herein for retaining a processing liquid on a surface of a semiconductor substrate. More specifically, improved methods are provided herein for retaining a puddle within a center region of a semiconductor substrate while the substrate is stationary, or rotating at relatively low rotational speeds. In the disclosed embodiments, a puddle is retained within a center region of the semiconductor substrate by a thin film, which is deposited within a peripheral edge region of the substrate before a processing liquid is dispensed within the center region of the substrate to form the puddle.

公开(公告)号：US12148624B2

公开(公告)日：2024-11-19

申请号：US17942387

申请日：2022-09-12

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Eric Chih-Fang Liu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia

IPC: H01L21/311

Abstract: Embodiments of improved process flows and methods are provided in the present disclosure to control fin height and channel area in a fin field effect transistor (FinFET) having gaps of variable CD. More specifically, the present disclosure provides improved transistor fabrication processes and methods that utilize a wet etch process, instead of a dry etch process, to remove the oxide material deposited within the gaps formed between the fins of a FinFET. By utilizing a wet etch process, the improved transistor fabrication processes and methods described herein provide a means to adjust or individually control the fin height of one or more the fins, thereby providing greater control over the channel area of the FinFET.

公开(公告)号：US12100598B2

公开(公告)日：2024-09-24

申请号：US17942369

申请日：2022-09-12

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Eric Chih-Fang Liu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia

IPC: H01L21/3105

CPC classification number: H01L21/31055

Abstract: The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.

公开(公告)号：US20240087909A1

公开(公告)日：2024-03-14

申请号：US17942387

申请日：2022-09-12

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Eric Chih-Fang Liu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia

IPC: H01L21/311

CPC classification number: H01L21/31111

Abstract: Embodiments of improved process flows and methods are provided in the present disclosure to control fin height and channel area in a fin field effect transistor (FinFET) having gaps of variable CD. More specifically, the present disclosure provides improved transistor fabrication processes and methods that utilize a wet etch process, instead of a dry etch process, to remove the oxide material deposited within the gaps formed between the fins of a FinFET. By utilizing a wet etch process, the improved transistor fabrication processes and methods described herein provide a means to adjust or individually control the fin height of one or more the fins, thereby providing greater control over the channel area of the FinFET.

公开(公告)号：US20240087907A1

公开(公告)日：2024-03-14

申请号：US17942369

申请日：2022-09-12

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Eric Chih-Fang Liu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia

IPC: H01L21/3105

CPC classification number: H01L21/31055

Abstract: The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.

公开(公告)号：US20240096638A1

公开(公告)日：2024-03-21

申请号：US17946609

申请日：2022-09-16

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia ,  Robert Clark

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/3213

CPC classification number: H01L21/31111 ,  H01L21/30604 ,  H01L21/32134

Abstract: Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material formed within features (e.g., trenches, holes, slits, etc.), and on more planar areas of a patterned substrate, when a critical dimension (CD) of the features is relatively small compared to the more planar areas of the patterned substrate. In the present disclosure, uniform wet etching is provided by ensuring that wall surfaces adjacent to the material being etched exhibit a neutral surface charge when exposed to the etch solution used to etch the material.

公开(公告)号：US20240087908A1

公开(公告)日：2024-03-14

申请号：US17942359

申请日：2022-09-12

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/3213

CPC classification number: H01L21/31111 ,  H01L21/30604 ,  H01L21/32134

Abstract: Embodiments of a wet etch process and method are disclosed to provide uniform etching of material formed within features (such as, e.g., trenches, holes, slits, etc.) having different critical dimension (CD). By combining a non-aqueous organic-based etch solution and an aqueous-based etch solution (either in series or in parallel) within a wet etch process, the disclosed embodiments utilize the opposing effects of CD-dependent etching to provide uniform etching of the material, regardless of CD.

公开(公告)号：US20230405642A1

公开(公告)日：2023-12-21

申请号：US18192279

申请日：2023-03-29

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Peter D'Elia ,  Ronald Nasman

IPC: B08B3/02 ,  H01L21/67 ,  H01L21/02 ,  B08B13/00 ,  F26B5/00

CPC classification number: B08B3/02 ,  H01L21/67028 ,  B08B2203/007 ,  B08B13/00 ,  F26B5/005 ,  H01L21/02057

Abstract: Improved processing systems and methods are provided for wet and dry processing of a semiconductor wafer. Provided is an enclosed chamber for processing a semiconductor wafer within a processing space and a drainage system for directing processing fluids out of the processing space. The enclosed chamber includes a top plate and a bottom plate, which physically confine the processing fluids within a relatively small, enclosed processing space. This forces the processing fluids to flow radially across the wafer surface(s) without the need to rotate the wafer. The drainage system contains a conduit that is downstream from the processing space and configured to retain a portion of a processing fluid dispensed within the processing space. The portion retained within the conduit provides a pressure resistance against the processing fluid(s) dispensed within the processing space to improve wet and dry processing of the wafer surfaces.

公开(公告)号：US11424123B2

公开(公告)日：2022-08-23

申请号：US16851414

申请日：2020-04-17

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko ,  Angelique Raley ,  Henan Zhang ,  Shan Hu ,  Subhadeep Kal

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/3065

Abstract: In certain embodiments, a method of forming a semiconductor device includes forming a patterned resist layer over a hard mask layer using an extreme ultraviolet (EUV) lithography process. The hard mask layer is disposed over a substrate. The method includes patterning the hard mask layer using the patterned resist layer as an etch mask. The method includes smoothing the hard mask layer by forming, using a first atomic layer etch step, a first layer by converting a first portion of the hard mask layer, and by removing, using a second atomic layer etch step, the first layer.

公开(公告)号：US12148625B2

公开(公告)日：2024-11-19

申请号：US17946609

申请日：2022-09-16

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia ,  Robert Clark

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/3213

Abstract: Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material formed within features (e.g., trenches, holes, slits, etc.), and on more planar areas of a patterned substrate, when a critical dimension (CD) of the features is relatively small compared to the more planar areas of the patterned substrate. In the present disclosure, uniform wet etching is provided by ensuring that wall surfaces adjacent to the material being etched exhibit a neutral surface charge when exposed to the etch solution used to etch the material.