公开(公告)号：US20170110434A1

公开(公告)日：2017-04-20

申请号：US15085458

申请日：2016-03-30

Applicant: TriQuint Semiconductor, Inc.

Inventor： Tarak A. Railkar ,  Kevin J. Anderson

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3164 ,  H01L23/3185 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/0901 ,  H01L2224/0912 ,  H01L2224/13005 ,  H01L2224/131 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/1369 ,  H01L2224/16227 ,  H01L2224/1705 ,  H01L2224/17106 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/8121 ,  H01L2224/81355 ,  H01L2224/81375 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81905 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/81904 ,  H01L2924/206 ,  H01L2924/014

Abstract: The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.

公开(公告)号：US09721867B1

公开(公告)日：2017-08-01

申请号：US14662091

申请日：2015-03-18

Applicant: Sandia Corporation ,  TriQuint Semiconductor, Inc.

Inventor： Cody M. Washburn ,  Timothy N. Lambert ,  David R. Wheeler ,  Christopher T. Rodenbeck ,  Tarak A. Railkar

IPC: B82Y40/00 ,  H01L21/02 ,  H01L23/373

CPC classification number: H01L23/3737 ,  H01L21/02115 ,  H01L21/02282 ,  H01L21/02318 ,  H01L23/373

Abstract: Various technologies presented herein relate to forming one or more heat dissipating structures (e.g., heat spreaders and/or heat sinks) on a substrate, wherein the substrate forms part of an electronic component. The heat dissipating structures are formed from graphene, with advantage being taken of the high thermal conductivity of graphene. The graphene (e.g., in flake form) is attached to a diazonium molecule, and further, the diazonium molecule is utilized to attach the graphene to material forming the substrate. A surface of the substrate is treated to comprise oxide-containing regions and also oxide-free regions having underlying silicon exposed. The diazonium molecule attaches to the oxide-free regions, wherein the diazonium molecule bonds (e.g., covalently) to the exposed silicon. Attachment of the diazonium plus graphene molecule is optionally repeated to enable formation of a heat dissipating structure of a required height.

公开(公告)号：US09585240B2

公开(公告)日：2017-02-28

申请号：US14062494

申请日：2013-10-24

Applicant: TriQuint Semiconductor, Inc.

Inventor： Thomas R. Landon, Jr. ,  Paul D. Bantz ,  Tarak A. Railkar

IPC: H05K1/16 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0204 ,  H05K1/0207 ,  H05K1/0215 ,  H05K1/0216 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/10416 ,  H05K2203/0191 ,  Y10T29/49155

Abstract: A laminate substrate may include a slug positioned within a cavity of a laminate core. The laminate substrate may have routing layers on either side of the laminate core, at least one of which is coplanar with an outer side of the slug. A capping layer may then be applied to the laminate substrate which is directly coupled with the slug and the routing layer. In embodiments, a dielectric layer may be coupled with the capping layer, and an additional routing layer may be coupled with the dielectric layer. Therefore, the routing layer may be an “inner” routing layer that is coplanar with, and coupled with, the slug.

Abstract translation: 层压基板可以包括位于层叠芯的空腔内的块状物。 层压基板可以在层叠芯的任一侧上具有路由层，其中至少一个与块的外侧共面。 然后可以将覆盖层施加到与块和路由层直接耦合的层压基板。 在实施例中，电介质层可以与覆盖层耦合，并且附加布线层可以与电介质层耦合。 因此，路由层可以是与块状体共面并与其结合的“内部”路由层。

公开(公告)号：US09659898B1

公开(公告)日：2017-05-23

申请号：US14603261

申请日：2015-01-22

Applicant: TriQuint Semiconductor, Inc.

Inventor： Tarak A. Railkar ,  Kevin J. Anderson ,  Walid Meliane ,  John M. Beall

IPC: H01L27/14 ,  H01L23/00 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L24/32 ,  H01L21/56 ,  H01L23/293 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/83951 ,  H01L2224/85801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: Embodiments of the present disclosure are directed towards apparatuses, systems, and methods for die attach coatings for semiconductor packages. In one embodiment, a die may be coupled with a substrate by a die attach and a coating may be applied to an edge of the die attach.

公开(公告)号：US20150116947A1

公开(公告)日：2015-04-30

申请号：US14062494

申请日：2013-10-24

Applicant: TriQuint Semiconductor, Inc.

Inventor： Thomas R. Landon, Jr. ,  Paul D. Bantz ,  Tarak A. Railkar

IPC: H05K1/02 ,  H05K3/44

CPC classification number: H05K1/0204 ,  H05K1/0207 ,  H05K1/0215 ,  H05K1/0216 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/10416 ,  H05K2203/0191 ,  Y10T29/49155

Abstract: A laminate substrate may include a slug positioned within a cavity of a laminate core. The laminate substrate may have routing layers on either side of the laminate core, at least one of which is coplanar with an outer side of the slug. A capping layer may then be applied to the laminate substrate which is directly coupled with the slug and the routing layer. In embodiments, a dielectric layer may be coupled with the capping layer, and an additional routing layer may be coupled with the dielectric layer. Therefore, the routing layer may be an “inner” routing layer that is coplanar with, and coupled with, the slug.

Abstract translation: 层压基板可以包括位于层叠芯的空腔内的块状物。 层压基板可以在层叠芯的任一侧上具有路由层，其中至少一个与块的外侧共面。 然后可以将覆盖层施加到与块和路由层直接耦合的层压基板。 在实施例中，电介质层可以与覆盖层耦合，并且附加布线层可以与电介质层耦合。 因此，路由层可以是与块状体共面并与其结合的“内部”路由层。

公开(公告)号：US08946894B2

公开(公告)日：2015-02-03

申请号：US13769729

申请日：2013-02-18

Applicant: TriQuint Semiconductor, Inc.

Inventor： Tarak A. Railkar ,  Deep C. Dumka

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H01L21/78

CPC classification number: H01L23/34 ,  H01L21/4882 ,  H01L21/78 ,  H01L23/373 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3735 ,  H01L23/3736 ,  H01L24/83 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.

Abstract translation: 本文公开了用于形成用于大功率半导体器件的封装的方法和装置。 包装可以包括设置在管芯和金属载体之间的多个不同的散热器层。 描述和要求保护其他实施例。

公开(公告)号：US20140231815A1

公开(公告)日：2014-08-21

申请号：US13769729

申请日：2013-02-18

Applicant: TRIQUINT SEMICONDUCTOR, INC.

Inventor： Tarak A. Railkar ,  Deep C. Dumka

IPC: H01L23/34 ,  H01L21/78

CPC classification number: H01L23/34 ,  H01L21/4882 ,  H01L21/78 ,  H01L23/373 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3735 ,  H01L23/3736 ,  H01L24/83 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.

Abstract translation: 本文公开了用于形成用于大功率半导体器件的封装的方法和装置。 包装可以包括设置在管芯和金属载体之间的多个不同的散热器层。 描述和要求保护其他实施例。

公开(公告)号：US09793237B2

公开(公告)日：2017-10-17

申请号：US15085458

申请日：2016-03-30

Applicant: TriQuint Semiconductor, Inc.

Inventor： Tarak A. Railkar ,  Kevin J. Anderson

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3164 ,  H01L23/3185 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/0901 ,  H01L2224/0912 ,  H01L2224/13005 ,  H01L2224/131 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/1369 ,  H01L2224/16227 ,  H01L2224/1705 ,  H01L2224/17106 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/8121 ,  H01L2224/81355 ,  H01L2224/81375 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81905 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/81904 ,  H01L2924/206 ,  H01L2924/014

Abstract: The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.

公开(公告)号：US09559034B2

公开(公告)日：2017-01-31

申请号：US14580147

申请日：2014-12-22

Applicant: TriQuint Semiconductor, Inc.

Inventor： Tarak A. Railkar ,  Deep C. Dumka

IPC: H01L21/44 ,  H01L23/34 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/34 ,  H01L21/4882 ,  H01L21/78 ,  H01L23/373 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3735 ,  H01L23/3736 ,  H01L24/83 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.

Abstract translation: 本文公开了用于形成用于大功率半导体器件的封装的方法和装置。 包装可以包括设置在管芯和金属载体之间的多个不同的散热器层。 描述和要求保护其他实施例。

公开(公告)号：US20160155681A9

公开(公告)日：2016-06-02

申请号：US14580147

申请日：2014-12-22

Applicant: TriQuint Semiconductor, Inc.

Inventor： Tarak A. Railkar ,  Deep C. Dumka

IPC: H01L23/34 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/34 ,  H01L21/4882 ,  H01L21/78 ,  H01L23/373 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3735 ,  H01L23/3736 ,  H01L24/83 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.