公开(公告)号：US11450385B2

公开(公告)日：2022-09-20

申请号：US16577309

申请日：2019-09-20

Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION

Inventor： Pierre-Emmanuel Gaillardon ,  Edouard Giacomin ,  Joao Vieira

IPC: G11C13/00 ,  G06N3/063 ,  G06N20/10 ,  G06F7/544 ,  G11C7/08 ,  G06F17/16 ,  G06N3/08

Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.

公开(公告)号：US20200098428A1

公开(公告)日：2020-03-26

申请号：US16577309

申请日：2019-09-20

Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION

Inventor： Pierre-Emmanuel Gaillardon ,  Edouard Giacomin ,  Joao Vieira

IPC: G11C13/00 ,  G06N3/063 ,  G06N3/08 ,  G06F7/544 ,  G11C7/08 ,  G06F17/16 ,  G06N20/10

Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.

公开(公告)号：US10348306B2

公开(公告)日：2019-07-09

申请号：US15916566

申请日：2018-03-09

Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION ,  École Polytechnique Fédérale de Lausanne

Inventor： Pierre-Emanuel Gaillardon ,  Xifan Tang ,  Gain Kim ,  Giovanni De Micheli ,  Edouard Giacomin

IPC: G11C13/00 ,  H03K19/173 ,  H01L45/00 ,  H01L27/24 ,  G06F17/50 ,  H03K19/177

Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.

公开(公告)号：US20180262197A1

公开(公告)日：2018-09-13

申请号：US15916566

申请日：2018-03-09

Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION ,  Ecole Polytechnique Federale de Lausanne

Inventor： Pierre-Emanuel Gaillardon ,  Xifan Tang ,  Gain Kim ,  Giovanni De Micheli ,  Edouard Giacomin

IPC: H03K19/173 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00 ,  H03K19/177 ,  G06F17/50

CPC classification number: H03K19/1737 ,  G06F17/5054 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1206 ,  H01L45/1253 ,  H03K19/1776

Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.