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公开(公告)号：US12117316B2
公开(公告)日：2024-10-15
申请号：US18159895
申请日：2023-01-26
Applicant: University of Utah Research Foundation
Inventor： Matthieu Couriol , Pierre-Emmanuel Gaillardon
CPC classification number: G01D5/16
Abstract: A sensor interface for a resistive sensor has an analog front end comprising. The analog front end has an analog input/output (I/O) sensor port to be coupled to the resistive sensor. An integration stage is coupled to the analog I/O sensor port to oscillate at an oscillation frequency proportional to a sensor resistance of the resistive sensor. The integration stage has a variable integrator capacitance to vary the oscillation frequency. A gain stage is coupled to the integration stage and has a variable gain to vary the oscillation frequency of the integration stage. The sensor interface also has a smart digital controller (SDC) coupled to the analog front end to compute the sensor resistance of the resistive sensor based on the oscillation frequency. In addition, the SDC automatically detects unstable oscillation in the integration stage and causes the variable gain and the variable integrator capacitance to change.
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公开(公告)号：US20200098428A1
公开(公告)日：2020-03-26
申请号：US16577309
申请日：2019-09-20
Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION
Inventor： Pierre-Emmanuel Gaillardon , Edouard Giacomin , Joao Vieira
Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.
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公开(公告)号：US20240255315A1
公开(公告)日：2024-08-01
申请号：US18159895
申请日：2023-01-26
Applicant: University of Utah Research Foundation
Inventor： Matthieu Couriol , Pierre-Emmanuel Gaillardon
IPC: G01D5/16
CPC classification number: G01D5/16
Abstract: A sensor interface for a resistive sensor has an analog front end comprising. The analog front end has an analog input/output (I/O) sensor port to be coupled to the resistive sensor. An integration stage is coupled to the analog I/O sensor port to oscillate at an oscillation frequency proportional to a sensor resistance of the resistive sensor. The integration stage has a variable integrator capacitance to vary the oscillation frequency. A gain stage is coupled to the integration stage and has a variable gain to vary the oscillation frequency of the integration stage. The sensor interface also has a smart digital controller (SDC) coupled to the analog front end to compute the sensor resistance of the resistive sensor based on the oscillation frequency. In addition, the SDC automatically detects unstable oscillation in the integration stage and causes the variable gain and the variable integrator capacitance to change.
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公开(公告)号：US11450385B2
公开(公告)日：2022-09-20
申请号：US16577309
申请日：2019-09-20
Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION
Inventor： Pierre-Emmanuel Gaillardon , Edouard Giacomin , Joao Vieira
Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.
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公开(公告)号：US20230244906A1
公开(公告)日：2023-08-03
申请号：US17592230
申请日：2022-02-03
Applicant: University of Utah Research Foundation
Inventor： Thomas Becnel , Pierre-Emmanuel Gaillardon
IPC: G06N3/04
CPC classification number: G06N3/0445
Abstract: Techniques for implementing a multi-branch neural network in an edge network are disclosed, where the multi-branch neural network is configured to infer latent features from fused sensor time series exogenous inputs. A multi-branch neural network is configured to include a LSTM branch and two FC branches. The multi-branch neural network is deployed on an edge node, which receives raw input from sensors. The raw input is fed into the LSTM branch and into the second FC branch. The raw input is fed into a normalization block that performs feature-wise normalization to generate normalized input. The normalized input is fed into the first FC block. The multi-branch neural network is used to generate a latent inference based on outputs provided by the LSTM branch and the two FC branches.
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Patent Agency Ranking
公开(公告)号：US20210376937A1
公开(公告)日：2021-12-02
申请号：US16888270
申请日：2020-05-29
Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION
Inventor： Thomas Becnel , Pierre-Emmanuel Gaillardon , Kerry Elizabeth Kelly
Abstract: A computer system for recursive calibration of a sensor network receives a first data communication from a first sensor node that is a neighbor to a calibrated sensor node. The computer system then updates a set of linear regressions between the first sensor node and a set of neighboring sensor nodes, which include the neighboring, calibrated sensor node. The computer system calibrates the first sensor node using an average of the set of linear regressions weighted by a correlation. When the first sensor node is calibrated, the computer system uses the calibrated first sensor node in calibration of a neighboring, uncalibrated sensor node. The computer system then gathers, at the first sensor node, a calibrated sensor reading.
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公开(公告)号：US12112820B2
公开(公告)日：2024-10-08
申请号：US17539923
申请日：2021-12-01
Applicant: University of Utah Research Foundation
Inventor： Aurelien Alacchi , Pierre-Emmanuel Gaillardon
CPC classification number: G11C29/4401 , G11C7/06 , G11C7/1057 , G11C7/1084 , G11C29/38 , G11C29/789
Abstract: Electronic devices and methods for single event effect mitigation are described. The device can include a processor, a memory cell, and an integrated particle sensor. The memory cell can comprise a substrate, a deep well coupled to the substrate, and a ground-coupled well coupled to the deep well. The integrated particle sensor can be coupled between the substrate and the deep well, and the ground-coupled well and the deep well. The integrated particle sensor can be operable to detect an ionizing particle generating the single event effect. The electronic device can be a field-programmable gate array. The method can include detecting an ionizing particle generating a single event effect at a memory cell of the electronic device, switching from the memory cell to a redundant memory cell associated with the memory cell when the single event effect is detected, and reconfiguring the memory cell based on the redundant memory cell.
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公开(公告)号：US20230297748A1
公开(公告)日：2023-09-21
申请号：US17695093
申请日：2022-03-15
Applicant: University of Utah Research Foundation
Inventor： Ganesh Gore , Xifan Tang , Pierre-Emmanuel Gaillardon
IPC: G06F30/347
CPC classification number: G06F30/347 , G06F2119/12
Abstract: Technology is disclosed related to methods and devices for reducing the top-level placement and routing runtime of a field-programmable gate arrays (FPGA). The method can comprise: generating a global signal netlist comprising feedthrough connections through non-adjacent FPGA modules; selecting a predefined signal connection pattern for the global signal netlist; generating pre-routed feedthrough connections based on the predefined signal connection pattern and the global signal netlist; and generating a pre-routed global signal netlist from the pre-routed feedthrough connections. The FPGA can comprise an FPGA module configured to send a pre-routed global signal to a non-adjacent FPGA module through a pre-routed feedthrough connection identified using a predefined signal connection pattern.
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公开(公告)号：US20230170038A1
公开(公告)日：2023-06-01
申请号：US17539923
申请日：2021-12-01
Applicant: University of Utah Research Foundation
Inventor： Aurelien Alacchi , Pierre-Emmanuel Gaillardon
CPC classification number: G11C29/4401 , G11C29/38 , G11C29/789 , G11C7/06 , G11C7/1057 , G11C7/1084
Abstract: Electronic devices and methods for single event effect mitigation are described. The device can include a processor, a memory cell, and an integrated particle sensor. The memory cell can comprise a substrate, a deep well coupled to the substrate, and a ground-coupled well coupled to the deep well. The integrated particle sensor can be coupled between the substrate and the deep well, and the ground-coupled well and the deep well. The integrated particle sensor can be operable to detect an ionizing particle generating the single event effect. The electronic device can be a field-programmable gate array.
The method can include detecting an ionizing particle generating a single event effect at a memory cell of the electronic device, switching from the memory cell to a redundant memory cell associated with the memory cell when the single event effect is detected, and reconfiguring the memory cell based on the redundant memory cell.-
公开(公告)号：US11251881B2
公开(公告)日：2022-02-15
申请号：US16888270
申请日：2020-05-29
Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATION
Inventor： Thomas Becnel , Pierre-Emmanuel Gaillardon , Kerry Elizabeth Kelly
Abstract: A computer system for recursive calibration of a sensor network receives a first data communication from a first sensor node that is a neighbor to a calibrated sensor node. The computer system then updates a set of linear regressions between the first sensor node and a set of neighboring sensor nodes, which include the neighboring, calibrated sensor node. The computer system calibrates the first sensor node using an average of the set of linear regressions weighted by a correlation. When the first sensor node is calibrated, the computer system uses the calibrated first sensor node in calibration of a neighboring, uncalibrated sensor node. The computer system then gathers, at the first sensor node, a calibrated sensor reading.
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