公开(公告)号：US20190373713A1

公开(公告)日：2019-12-05

申请号：US16543609

申请日：2019-08-18

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Kai-Ming YANG ,  Pu-Ju LIN ,  Cheng-Ta KO ,  Yu-Hua CHEN

IPC: H05K1/02 ,  H05K1/11

Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.

公开(公告)号：US20190239362A1

公开(公告)日：2019-08-01

申请号：US16379816

申请日：2019-04-10

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming YANG ,  Chen-Hao LIN ,  Cheng-Ta KO ,  John Hon-Shing LAU ,  Yu-Hua CHEN ,  Tzyy-Jang TSENG

IPC: H05K3/40 ,  H05K1/14 ,  H05K1/11 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/18

CPC classification number: H05K3/4038 ,  H01L21/4846 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

公开(公告)号：US20220071010A1

公开(公告)日：2022-03-03

申请号：US17448893

申请日：2021-09-26

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Cheng-Ta KO ,  Pu-Ju LIN ,  Chi-Hai KUO ,  Shao-Chien LEE ,  Ming-Ru CHEN ,  Cheng-Chung LO

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/00

Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.

公开(公告)号：US20220375919A1

公开(公告)日：2022-11-24

申请号：US17818006

申请日：2022-08-08

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming YANG ,  Chen-Hao LIN ,  Cheng-Ta KO ,  John Hon-Shing LAU ,  Yu-Hua CHEN ,  Tzyy-Jang TSENG

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

Abstract: A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.

公开(公告)号：US20210273356A1

公开(公告)日：2021-09-02

申请号：US17322906

申请日：2021-05-18

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Pei-Wei WANG ,  Ching-Ho HSIEH ,  Shao-Chien LEE ,  Kuo-Wei LI

IPC: H01R12/62 ,  H05K1/02 ,  H05K1/14 ,  H05K1/11 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

Abstract: A circuit board structure has a first flexible circuit board, a second flexible circuit board, and a rigid board structure. The first flexible circuit board has a first dielectric layer and a first conductive circuit. The second flexible circuit board has a second dielectric layer and a second conductive circuit. The rigid board structure connects the first flexible circuit board and the second flexible circuit board. The rigid board structure has a third dielectric layer and a third conductive circuit. A dielectric loss value of the third dielectric layer is less than that of each of the first dielectric layer and the second dielectric layer. The third conductive circuit is electrically connected to the first and second conductive circuits.

公开(公告)号：US20190139907A1

公开(公告)日：2019-05-09

申请号：US16240806

申请日：2019-01-07

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju LIN ,  Cheng-Ta KO ,  Yu-Hua CHEN ,  Tzyy-Jang TSENG ,  Ra-Min TAIN

IPC: H01L23/00 ,  H01L23/66

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US20240306298A1

公开(公告)日：2024-09-12

申请号：US18668275

申请日：2024-05-20

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Cheng-Ta KO ,  Pu-Ju LIN ,  Chi-Hai KUO ,  Shao-Chien LEE ,  Ming-Ru CHEN ,  Cheng-Chung LO

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0306 ,  H05K3/0067 ,  H05K3/0094

Abstract: A manufacturing method of a circuit board structure includes the following steps. A first sub-circuit board having an upper surface and a lower surface opposite to each other and including at least one conductive through hole is provided. A second sub-circuit board including at least one conductive through hole is provided on the upper surface of the first sub-circuit board. A third sub-circuit board including at least one conductive through hole is provided on the lower surface of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are laminated so that at least two of their conductive through holes are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.

公开(公告)号：US20210159191A1

公开(公告)日：2021-05-27

申请号：US17170736

申请日：2021-02-08

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju LIN ,  Cheng-Ta KO ,  Yu-Hua CHEN ,  Tzyy-Jang TSENG ,  Ra-Min TAIN

IPC: H01L23/00 ,  H01L23/66 ,  H01L23/16

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US20200266155A1

公开(公告)日：2020-08-20

申请号：US16866530

申请日：2020-05-04

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju LIN ,  Cheng-Ta KO ,  Yu-Hua CHEN ,  Tzyy-Jang TSENG ,  Ra-Min TAIN

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/66

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US20200235272A1

公开(公告)日：2020-07-23

申请号：US16842716

申请日：2020-04-07

Applicant: Unimicron Technology Corp.

Inventor： Pei-Wei WANG ,  Cheng-Ta KO ,  Yu-Hua CHEN ,  De-Shiang LIU ,  Tzyy-Jang TSENG

IPC: H01L33/62

Abstract: A manufacturing method of a light emitting device package structure is provided. The method includes following operations: (i) providing a circuit redistribution structure; (ii) providing a first substrate; (iii) forming a circuit layer structure over the first substrate, wherein the circuit layer structure includes a first circuit layer; (iv) before or after operation (iii), placing a light emitting device between the first substrate and the circuit layer structure or over the circuit layer structure, wherein the light emitting device is electrically connected with the first circuit layer; and (v) placing the circuit redistribution structure over the light emitting device, wherein the circuit redistribution structure includes a first redistribution layer, a second redistribution layer, and a chip, and the first redistribution layer includes a second circuit layer and a conductive contact that contacts the second circuit layer.