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公开(公告)号:US20210074633A1
公开(公告)日:2021-03-11
申请号:US17100932
申请日:2020-11-22
Applicant: Unimicron Technology Corp.
Inventor: Chien-Chou CHEN , Chun-Hsien CHIEN , Wen-Liang YEH , Wei-Ti LIN
IPC: H01L23/522 , H01L23/04 , H01L23/00 , H01L21/50
Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
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公开(公告)号:US20180014404A1
公开(公告)日:2018-01-11
申请号:US15273672
申请日:2016-09-22
Applicant: Unimicron Technology Corp.
Inventor: Yu-Chung HSIEH , Chun-Hsien CHIEN , Wei-Ti LIN , Yu-Hua CHEN
CPC classification number: H05K1/0306 , H05K1/0271 , H05K3/0052 , H05K3/4605 , H05K3/4688 , H05K2201/0154 , H05K2201/0175 , H05K2201/068 , H05K2201/09845
Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.
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