公开(公告)号：US20230282594A1

公开(公告)日：2023-09-07

申请号：US17688099

申请日：2022-03-07

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Chin-Tien Chiu ,  Jia Li ,  Dongpeng Xue ,  Huirong Zhang ,  Guocheng Zhong ,  Xiaohui Wang ,  Hua Tan

IPC: H01L23/544 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L27/11578

Abstract: A semiconductor wafer includes semiconductor dies and laser grooves formed in the scribe lines along the long edges of the semiconductor dies. A laser groove extends between the long edges of two adjacent semiconductor dies to encompass the corners of the two adjacent semiconductor dies. This prevents die cracking, for example during backgrind of the wafer. Moreover, the absence of laser grooves along the short edges of the semiconductor dies prevents die cracking, for example along short edges of dies overhanging empty space that are stressed during portions of the packaging process.

公开(公告)号：US20220406726A1

公开(公告)日：2022-12-22

申请号：US17354119

申请日：2021-06-22

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Jiandi Du ,  Binbin Zheng ,  Rui Guo ,  Chin-Tien Chiu ,  Zengyu Zhou ,  Fen Yu

IPC: H01L23/552 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.

公开(公告)号：US11425817B2

公开(公告)日：2022-08-23

申请号：US17107847

申请日：2020-11-30

Applicant: Western Digital Technologies, Inc.

Inventor： Shineng Ma ,  Xuyi Yang ,  Chih-Chin Liao ,  Chin-Tien Chiu ,  Jinxiang Huang

IPC: H05K1/14 ,  H05K5/02 ,  H05K7/00 ,  H05K7/14 ,  G06K7/00 ,  G06K19/06 ,  H01R33/00 ,  H05K1/11 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18

Abstract: A memory card includes a memory card body dimensioned to house at least one integrated circuit die package. The memory card body, in certain embodiments, includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card also includes a contact pad disposed on at least one side surface of the plurality of side surfaces. The contact pad includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.

公开(公告)号：US11355485B2

公开(公告)日：2022-06-07

申请号：US16818426

申请日：2020-03-13

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Yazhou Zhang ,  Chin-Tien Chiu ,  Shineng Ma

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor die is provided. The semiconductor die includes: at least one complementary metal oxide semiconductor (CMOS) circuit module electrically coupled to at least one memory die, the at least one memory die being separated from the semiconductor die; and a controller module electrically coupled to the CMOS circuit module and configured to control the at least one CMOS circuit module and the at least one memory die. A semiconductor package is also provided.

公开(公告)号：US11257785B2

公开(公告)日：2022-02-22

申请号：US16818817

申请日：2020-03-13

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Cong Zhang ,  Chin-Tien Chiu ,  Xuyi Yang ,  Yazhou Zhang

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.

公开(公告)号：US20210366875A1

公开(公告)日：2021-11-25

申请号：US17137990

申请日：2020-12-30

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Xiaofeng Di ,  Junrong Yan ,  CheeKeong Chin ,  Weili Wang ,  Xin Lu ,  Qi Deng ,  Chaur Yang Ng ,  Cong Zhang ,  Chenlin Yang ,  Chin-Tien Chiu

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor device includes a vertical column of wire bonds on substrate contact fingers of the device. Semiconductor dies are mounted on a substrate, and electrically coupled to the substrate such that groups of semiconductor dies may have bond wires extending to the same contact finger on the substrate. By bonding those wires to the contact finger in a vertical column, as opposed to separate, side-by-side wire bonds on the contact finger, an area of the contact finger may be reduced.

公开(公告)号：US12154860B2

公开(公告)日：2024-11-26

申请号：US17348989

申请日：2021-06-16

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Zhongli Ji ,  Ning Ye ,  Chin-Tien Chiu ,  Fen Yu

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A method of forming a semiconductor device includes forming vertical contact fingers in a substrate having side portions that are flexible. Contact fingers are formed near one or more edges of the flexible side portions of the substrate. After semiconductor dies are mounted to and electrically coupled to the substrate, the semiconductor device may be encapsulated by placing the device in a mold chase including upper and lower mold plates. The lower mold plate is sized smaller than the substrate so that the flexible side portions of the substrate including the contact fingers fold vertically upward to fit within the mold.

公开(公告)号：US11784135B2

公开(公告)日：2023-10-10

申请号：US17354119

申请日：2021-06-22

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Jiandi Du ,  Binbin Zheng ,  Rui Guo ,  Chin-Tien Chiu ,  Zengyu Zhou ,  Fen Yu

IPC: H01L23/552 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1357 ,  H01L2224/13144 ,  H01L2224/13647 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/3025

Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.

公开(公告)号：US20220415750A1

公开(公告)日：2022-12-29

申请号：US17902641

申请日：2022-09-02

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Jiandi Du ,  Yazhou Zhang ,  Binbin Zheng ,  Sundarraj Chandran ,  Wenbin Qu ,  Chin-Tien Chiu

IPC: H01L23/38 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065

Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.

公开(公告)号：US11456279B2

公开(公告)日：2022-09-27

申请号：US16887107

申请日：2020-05-29

Applicant: Western Digital Technologies, Inc.

Inventor： Cong Zhang ,  Chin-Tien Chiu ,  Xuyi Yang ,  Qi Deng

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065

Abstract: A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.