公开(公告)号：US20250151255A1

公开(公告)日：2025-05-08

申请号：US19016032

申请日：2025-01-10

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ping HSIAO ,  Cheol-Soo PARK ,  Chun-Hung CHENG ,  Wei-Chieh CHUANG ,  Wei-Chao CHOU ,  Yen-Min JUAN

IPC: H10B12/00 ,  H01G4/008 ,  H01G4/01

Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.

公开(公告)号：US20220415891A1

公开(公告)日：2022-12-29

申请号：US17592751

申请日：2022-02-04

Applicant: Winbond Electronics Corp.

Inventor： Yu-Ping HSIAO ,  Cheol-Soo PARK ,  Chun-Hung CHENG ,  Wei-Chieh CHUANG ,  Wei-Chao CHOU ,  Yen-Min JUAN

IPC: H01L27/108 ,  H01G4/01 ,  H01G4/008

Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.

公开(公告)号：US20210242209A1

公开(公告)日：2021-08-05

申请号：US17166583

申请日：2021-02-03

Applicant: Winbond Electronics Corp.

Inventor： Cheol-Soo PARK ,  Ming-Tang CHEN

IPC: H01L27/108

Abstract: A DRAM device and its manufacturing method are provided. The DRAM device includes an interlayer dielectric layer and capacitor units framed on a substrate. The interlayer dielectric layer has capacitor unit accommodating through holes and includes a first support layer, a composite dielectric layer, and a second support layer sequentially formed on the substrate. The composite dielectric layer includes at least one first insulating layer and second insulating layer alternately stacked. Each capacitor unit accommodating through hole forms a first opening in the second insulating layer and forms a second opening communicating with the first opening in the first insulating layer. The second opening is wider than the first opening. The capacitor units are formed in the capacitor unit accommodating through holes. The top of the capacitor unit is higher than the top surface of the interlayer dielectric layer and defines a recessed region.