公开(公告)号：US09070600B2

公开(公告)日：2015-06-30

申请号：US13983655

申请日：2012-01-31

Applicant: Hiromitsu Katsui ,  Yoshimasa Chikama ,  Wataru Nakamura ,  Tetsunori Tanaka ,  Kenichi Kitoh

Inventor： Hiromitsu Katsui ,  Yoshimasa Chikama ,  Wataru Nakamura ,  Tetsunori Tanaka ,  Kenichi Kitoh

IPC: H01L29/12 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49 ,  G02F1/1368

CPC classification number: H01L27/1244 ,  G02F1/1368 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869

Abstract: A drain electrode (17) includes (i) a lower drain electrode (17a) stacked on a semiconductor layer (14) so as to partially cover an upper surface of the semiconductor layer (14) and (ii) an upper drain electrode (17b). The semiconductor layer (14), the lower drain electrode (17a), and the upper drain electrode (17b) form steps. In a step part where the steps are formed, a distance between a periphery of the lower drain electrode (17a) and a periphery of the upper drain electrode (17b) is more than 0.4 μm but less than 1.5 μm.

Abstract translation: 漏电极（17）包括：（i）层叠在半导体层（14）上的下漏电极（17a），以部分地覆盖半导体层（14）的上表面，以及（ii）上漏电极（17b） ）。 半导体层（14），下漏电极（17a）和上漏电极（17b）形成台阶。 在形成台阶的台阶部分中，下漏电极（17a）的周边与上漏电极（17b）的周边之间的距离大于0.4μm但小于1.5μm。

公开(公告)号：US08940566B2

公开(公告)日：2015-01-27

申请号：US13883014

申请日：2011-11-01

Applicant: Okifumi Nakagawa ,  Yoshimasa Chikama ,  Takeshi Hara ,  Hiromitsu Katsui

Inventor： Okifumi Nakagawa ,  Yoshimasa Chikama ,  Takeshi Hara ,  Hiromitsu Katsui

IPC: H01L21/00 ,  H01L29/66 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L29/66969 ,  G02F1/136227 ,  G02F2001/136231 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/7869

Abstract: The semiconductor device (100) according to the present invention includes a gate electrode (102) of a TFT, a gate insulating layer (103) formed on the gate electrode (102), an oxide semiconductor layer (107) disposed on the gate insulating layer (103), a protecting layer (108) formed on the oxide semiconductor layer (107) by a spin-on-glass technique, and a source electrode (105) and a drain electrode (106) disposed on the protecting layer (108). Via a first contact hole (131) formed in the protecting layer (108), the source electrode (105) is electrically connected to the oxide semiconductor layer (104), and via a second contact hole (132), the drain electrode (106) is electrically connected to the oxide semiconductor layer (104).

Abstract translation: 根据本发明的半导体器件（100）包括TFT的栅极（102），形成在栅电极（102）上的栅极绝缘层（103），设置在栅绝缘层上的氧化物半导体层（107） 层（103），通过旋涂玻璃技术形成在氧化物半导体层（107）上的保护层（108）以及设置在保护层（108）上的源电极（105）和漏电极（106） ）。 通过形成在保护层（108）中的第一接触孔（131），源电极（105）与氧化物半导体层（104）电连接，经由第二接触孔（132），漏电极 ）与氧化物半导体层（104）电连接。

公开(公告)号：US08829513B2

公开(公告)日：2014-09-09

申请号：US13391638

申请日：2010-03-29

Applicant: Yoshifumi Ota ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Kazuo Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Hinae Mizuno

Inventor： Yoshifumi Ota ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Kazuo Nakagawa ,  Yuuji Mizuno ,  Michiko Takei ,  Yoshiyuki Harumoto

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/32 ,  H01L33/00 ,  G02F1/1368

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  H01L27/3258 ,  H01L33/0041

Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01≦Zn/(In+Zn)≦0.22.

Abstract translation: 本发明提供实现电性能和工艺电阻优异的TFT的氧化物半导体，包括由氧化物半导体形成的沟道层的TFT以及配备有TFT的显示装置。 本发明的氧化物半导体是用于薄膜晶体管的氧化物半导体，其中氧化物半导体包含Ga（镓），In（铟），Zn（锌）和O（氧）作为构成原子，氧化物半导体 Zn原子组成满足0.01＆nlE; Zn /（In + Zn）＆nlE; 0.22。

公开(公告)号：US08481373B2

公开(公告)日：2013-07-09

申请号：US13383220

申请日：2010-03-16

Applicant: Tohru Okabe ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Takeshi Hara

Inventor： Tohru Okabe ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Takeshi Hara

IPC: H01L21/336

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/42384

Abstract: A method for manufacturing a thin film transistor substrate includes a step of forming a gate electrode (11a) and a first interconnect on a substrate (10), a step of forming a gate insulating film (12a) having a contact hole at a position overlapping the first interconnect, a step of forming a source electrode (13a) and a drain electrode (13b) overlapping the gate electrode (11a) and separated apart from each other, and a second interconnect connected via the contact hole to the first interconnect, a step of successively forming an oxide semiconductor film (14) and a second insulating film (15), and thereafter, patterning the second insulating film (15) to form an interlayer insulating film (15a), and a step of reducing the resistance of the oxide semiconductor film (14) exposed through the interlayer insulating film (15a) to form a pixel electrode (14b).

Abstract translation: 制造薄膜晶体管基板的方法包括在基板（10）上形成栅极（11a）和第一布线的步骤，在重叠的位置形成具有接触孔的栅极绝缘膜（12a）的步骤 所述第一互连，形成与所述栅电极（11a）重叠并分离的源电极（13a）和漏电极（13b）的步骤，以及经由所述接触孔与所述第一互连件连接的第二互连件， 连续地形成氧化物半导体膜（14）和第二绝缘膜（15）的步骤，然后对第二绝缘膜（15）进行图案化以形成层间绝缘膜（15a），并且降低 氧化物半导体膜（14）通过层间绝缘膜（15a）露出以形成像素电极（14b）。

公开(公告)号：US20120218485A1

公开(公告)日：2012-08-30

申请号：US13501534

申请日：2010-07-26

Applicant: Yoshimasa Chikama ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yuuji Mizuno ,  Hinae Mizuno ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto

Inventor： Yoshimasa Chikama ,  Hirohiko Nishiki ,  Yoshifumi Ohta ,  Yuuji Mizuno ,  Hinae Mizuno ,  Takeshi Hara ,  Tetsuya Aita ,  Masahiko Suzuki ,  Michiko Takei ,  Okifumi Nakagawa ,  Yoshiyuki Harumoto

IPC: G02F1/136 ,  H01L33/08 ,  H01L29/786

CPC classification number: H01L27/1255 ,  G02F1/136213 ,  G02F2201/40 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: An active matrix substrate includes a plurality of pixels arranged in a matrix, a plurality of capacitor lines (11b) extending in one of directions in which the pixels are aligned and in parallel to each other, a plurality of TFTs (5), one for each of the pixels, a protective film (16a) covering the TFTs (5), a plurality of pixel electrodes (18a) arranged in a matrix on the protective film (16a) and connected to the respective corresponding TFTs (5), and a plurality of auxiliary capacitors (6), one for each of the pixels. Each of the auxiliary capacitors (6) includes the corresponding capacitor line (11b), the corresponding pixel electrode (18a), and the protective film (16a) between the corresponding capacitor line (11b) and the corresponding pixel electrode (18a).

Abstract translation: 有源矩阵基板包括以矩阵形式布置的多个像素，多个电容线（11b），其中像素彼此排列并且彼此平行的方向中的一个方向延伸;多个TFT（5），一个用于 每个像素，覆盖TFT（5）的保护膜（16a），在保护膜（16a）上以矩阵布置并连接到相应的TFT（5）的多个像素电极（18a）和 多个辅助电容器（6），每个像素一个。 每个辅助电容器（6）包括相应的电容器线（11b），对应的像素电极（18a）和相应的电容器线（11b）和相应的像素电极（18a）之间的保护膜（16a）。

公开(公告)号：US20120199891A1

公开(公告)日：2012-08-09

申请号：US13499960

申请日：2010-10-04

Applicant: Masahiko Suzuki ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Yoshifumi Ohta ,  Tetsuya Aita ,  Okifumi Nakagawa ,  Takeshi Hara

Inventor： Masahiko Suzuki ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Yoshifumi Ohta ,  Tetsuya Aita ,  Okifumi Nakagawa ,  Takeshi Hara

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  H01L29/66969 ,  H01L29/78606

Abstract: A semiconductor device includes: a gate electrode (3) arranged on a substrate (1); a gate insulating layer (5) deposited over the gate electrode (3); an island of an oxide semiconductor layer (7) formed on the gate insulating layer (5) and including a channel region (7c) and first and second contact regions (7s, 7d) located on right- and left-hand sides of the channel region (7c); a source electrode (11) electrically connected to the first contact region (7s); a drain electrode (13) electrically connected to the second contact region (7d); and a protective layer (9) which is arranged on, and in contact with, the oxide semiconductor layer (7). The protective layer (9) covers the channel region (7c) on the surface of the oxide semiconductor layer (7), the sidewalls (7e) thereof located in a channel width direction with respect to the channel region (7c), and other portions (7f) thereof between the channel region (7c) and the sidewalls (7e). As a result, the hysteresis characteristic of a TFT that uses an oxide semiconductor can be improved and its reliability can be increased.

Abstract translation: 半导体器件包括：布置在衬底（1）上的栅电极（3）; 沉积在栅电极（3）上的栅极绝缘层（5）; 形成在所述栅极绝缘层（5）上并且包括沟道区（7c）的氧化物半导体层（7）的岛和位于所述沟道的右侧和左侧的第一和第二接触区（7s，7d） 区域（7c）; 电连接到第一接触区域（7s）的源电极（11）; 电连接到第二接触区域（7d）的漏电极（13）; 以及设置在所述氧化物半导体层（7）上并与所述氧化物半导体层（7）接触的保护层（9）。 保护层（9）覆盖氧化物半导体层（7）的表面上的沟道区域（7c），其侧壁（7e）相对于沟道区域（7c）位于沟道宽度方向，其它部分 （7f）之间的沟道区域（7f）。 结果，可以提高使用氧化物半导体的TFT的滞后特性，并且可以提高其可靠性。

公开(公告)号：US20120091452A1

公开(公告)日：2012-04-19

申请号：US13377824

申请日：2010-03-10

Applicant: Yoshifumi Ohta ,  Go Mori ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Hara

Inventor： Yoshifumi Ohta ,  Go Mori ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Hara

IPC: H01L29/786 ,  H01L21/34

CPC classification number: H01L29/22 ,  G02F1/1368 ,  G02F2202/10 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.

Abstract translation: 本发明提供一种能够实现具有稳定晶体管特性的薄膜晶体管的氧化物半导体，具有由氧化物半导体形成的沟道层的薄膜晶体管及其制造方法，以及配备有该薄膜晶体管的显示装置。 本发明的氧化物半导体是薄膜晶体管的氧化物半导体。 氧化物半导体包括铟，镓，锌和氧作为构成原子，并且氧化物半导体的氧含量为化学计量条件的87％至95％，以原子单位计为100％。

公开(公告)号：US20090141438A1

公开(公告)日：2009-06-04

申请号：US12063152

申请日：2006-10-30

Applicant: Tetsuya Aita ,  Yoshimasa Chikama

Inventor： Tetsuya Aita ,  Yoshimasa Chikama

IPC: H05K1/00 ,  G06F1/16

CPC classification number: H05K3/323 ,  G02F1/13452 ,  H01L24/16 ,  H01L24/83 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H05K3/3452 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0989 ,  H05K2201/10674 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/05599

Abstract: An electrode connection structure including a first circuit component including a resin plate, a barrier film stacked on a surface of the resin plate, a circuit section formed on the barrier film and a first electrode provided on the surface of the resin plate on which the barrier film is stacked, and a second circuit component arranged to face the first circuit component and having a second electrode facing the first electrode, wherein the first and second electrodes are electrically connected via pressure applied thereto in the directions approaching each other and a portion of the barrier film surrounding the first electrode is at least partially removed from the surface of the resin plate.

Abstract translation: 一种电极连接结构，包括：第一电路部件，包括树脂板，层叠在树脂板的表面上的阻挡膜，形成在阻挡膜上的电路部分和设置在树脂板的表面上的第一电极， 并且第二电路部件布置成面向第一电路部件并且具有面向第一电极的第二电极，其中第一和第二电极经由施加到其上的压力在彼此接近的方向上电连接，并且部分 围绕第一电极的阻挡膜至少部分地从树脂板的表面去除。

公开(公告)号：US09024311B2

公开(公告)日：2015-05-05

申请号：US13379670

申请日：2010-04-06

Applicant: Takeshi Hara ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Kazuo Nakagawa ,  Yoshifumi Ohta ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Yoshiyuki Miyajima ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Hinae Mizuno

Inventor： Takeshi Hara ,  Hirohiko Nishiki ,  Yoshimasa Chikama ,  Kazuo Nakagawa ,  Yoshifumi Ohta ,  Tetsuya Aita ,  Masahiko Suzuki ,  Okifumi Nakagawa ,  Yoshiyuki Miyajima ,  Yuuji Mizuno ,  Michiko Takei ,  Yoshiyuki Harumoto

IPC: H01L29/786 ,  H01L21/336 ,  H01L27/12

CPC classification number: H01L27/1288 ,  H01L27/1225 ,  H01L29/7869

Abstract: The present invention provides a thin film transistor including an oxide semiconductor layer (4) for electrically connecting a signal electrode (6a) and a drain electrode (7a), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer (6b) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer (6b) being in touch with the signal electrode (6a) and the oxide semiconductor layer (4) and separating the signal electrode (6a) from the oxide semiconductor layer (4). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.

Abstract translation: 本发明提供了一种薄膜晶体管，其包括用于电连接信号电极（6a）和漏电极（7a）的氧化物半导体层（4），所述氧化物半导体层由氧化物半导体制成; 以及由选自Ti，Mo，W，Nb，Ta，Cr，氮化物中的至少一种及其合金制成的阻挡层（6b），阻挡层（6b）与信号电极 （6a）和氧化物半导体层（4），并且将信号电极（6a）与氧化物半导体层（4）分离。 由于这种结构，薄膜晶体管可以在第一电极和沟道层之间形成并保持欧姆接触，从而成为具有良好性能的薄膜晶体管。

公开(公告)号：US20140151682A1

公开(公告)日：2014-06-05

申请号：US13810113

申请日：2011-04-13

Applicant: Yuichi Saito ,  Yohsuke Kanzaki ,  Yudai Takanishi ,  Tetsuya Okamoto ,  Yoshiki Nakatani ,  Yoshimasa Chikama

Inventor： Yuichi Saito ,  Yohsuke Kanzaki ,  Yudai Takanishi ,  Tetsuya Okamoto ,  Yoshiki Nakatani ,  Yoshimasa Chikama

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1225 ,  G02F1/133345 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136231 ,  G02F2001/136236 ,  G02F2001/136295 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/44 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/53233 ,  H01L23/53238 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a circuit board having excellent productivity, particularly a circuit board having excellent productivity with respect to a semiconductor layer and source layer forming step, a display device, and a process for producing a circuit board. The circuit board of the present invention is a circuit board including an oxide semiconductor layer and an electrode connected to the oxide semiconductor layer, wherein the electrode is formed by essentially laminating a layer made of a metal other than copper and a layer containing copper.

Abstract translation: 本发明提供一种具有优异生产率的电路板，特别是相对于半导体层和源层形成步骤具有优异的生产率的电路板，显示装置和用于制造电路板的工艺。 本发明的电路基板是包括氧化物半导体层和连接到氧化物半导体层的电极的电路板，其中电极通过基本上层压由铜以外的金属制成的层和含有铜的层而形成。