公开(公告)号：US07723234B2

公开(公告)日：2010-05-25

申请号：US11562443

申请日：2006-11-22

Applicant: Suryadevara V. Babu ,  Anita Natarajan ,  Sharath Hegde

Inventor： Suryadevara V. Babu ,  Anita Natarajan ,  Sharath Hegde

IPC: H01L21/302

CPC classification number: H01L21/3212 ,  B81C1/00595 ,  B81C1/00611 ,  B81C2201/0104 ,  B81C2201/0126 ,  C09G1/02 ,  C09K3/1463

Abstract: A method of removing polysilicon in preference to silicon dioxide and/or silicon nitride by chemical mechanical polishing. The method removes polysilicon from a surface at a high removal rate while maintaining a high selectivity of polysilicon to silicon dioxide and/or a polysilicon to silicon nitride. The method is particularly suitable for use in the fabrication of MEMS devices.

Abstract translation: 通过化学机械抛光优选去除二氧化硅和/或氮化硅的多晶硅的方法。 该方法以高去除率从表面去除多晶硅，同时保持多晶硅对二氧化硅和/或多晶硅与氮化硅的高选择性。 该方法特别适用于MEMS器件的制造。

公开(公告)号：US09416298B2

公开(公告)日：2016-08-16

申请号：US14402975

申请日：2013-05-21

Applicant: BASF SE

Inventor： Yuzhuo Li ,  Bastian Marten Noller ,  Christophe Gillot ,  Diana Franz

IPC: C09G1/02 ,  H01L21/304 ,  H01L21/302 ,  H01L21/321 ,  H01L21/461 ,  H01L21/306 ,  H01L21/02

CPC classification number: C09G1/02 ,  B81C2201/0121 ,  B81C2201/0123 ,  B81C2201/0126 ,  H01L21/02024 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/461

Abstract: A process for the manufacture of semiconductor devices comprising the chemical-mechanical polishing of a substrate or layer containing at least one III-V material in the presence of a chemical-mechanical polishing composition (Q1) comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) at least one amphiphilic non-ionic surfactant having (b1) at least one hydrophobic group; and (b2) at least one hydrophilic group selected from the group consisting of polyoxyalkylene groups comprising (b22) oxyalkylene monomer units other than oxyethylene monomer units; and (M) an aqueous medium.

Abstract translation: 一种用于制造半导体器件的方法，包括在化学机械抛光组合物（Q1）的存在下对包含至少一种III-V材料的基底或层进行化学机械抛光，所述化学机械抛光组合物包含（A）无机颗粒，有机颗粒， 或其混合物或复合物，（B）至少一种具有（b1）至少一个疏水基团的两亲性非离子表面活性剂; 和（b2）至少一种选自包含（b22）氧化烯单体单元以外的氧化烯单体单元的聚氧化烯基的亲水基团; 和（M）水性介质。

公开(公告)号：US09287050B2

公开(公告)日：2016-03-15

申请号：US13413889

申请日：2012-03-07

Applicant: Tomohiro Saito

Inventor： Tomohiro Saito

IPC: H01L29/84 ,  H01G5/18 ,  B81C1/00

CPC classification number: H01G5/18 ,  B81B2201/018 ,  B81B2201/0221 ,  B81B2203/0109 ,  B81C1/00611 ,  B81C2201/0126

Abstract: According to one embodiment, a MEMS includes a first electrode, a first auxiliary structure and a second electrode. The first electrode is provided on a substrate. The first auxiliary structure is provided on the substrate and adjacent to the first electrode. The first auxiliary structure is in an electrically floating state. The second electrode is provided above the first electrode and the first auxiliary structure, and is driven in a direction of the first electrode.

Abstract translation: 根据一个实施例，MEMS包括第一电极，第一辅助结构和第二电极。 第一电极设置在基板上。 第一辅助结构设置在基板上并与第一电极相邻。 第一辅助结构处于电浮动状态。 第二电极设置在第一电极和第一辅助结构之上，并且沿第一电极的方向被驱动。

公开(公告)号：US20170113925A1

公开(公告)日：2017-04-27

申请号：US15297662

申请日：2016-10-19

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Patrice REY

IPC: B81C1/00

CPC classification number: B81C1/0023 ,  B81C1/00333 ,  B81C2201/0108 ,  B81C2201/0109 ,  B81C2201/0126 ,  B81C2201/014 ,  B81C2201/056 ,  B81C2203/01 ,  B81C2203/0792

Abstract: Method for encapsulation of a microelectronic component, including making of a portion of sacrificial material on a front face of a first substrate in which the component is intended to be made, then making of a cover encapsulating the portion of sacrificial material, then making of the component by etching the first substrate from its back face, such that part of the component is arranged to face the portion of sacrificial material and such that the portion of sacrificial material is accessible from a back face of the component, then elimination of the portion of sacrificial material by etching from the back face of the component, then securing of the back face of the component to a second substrate.

公开(公告)号：US20150175845A1

公开(公告)日：2015-06-25

申请号：US14402975

申请日：2013-05-21

Applicant: BASF SE

Inventor： Yuzhuo Li ,  Bastian Marten Noller ,  Christophe Gillot ,  Diana Franz

IPC: C09G1/02 ,  H01L21/306

CPC classification number: C09G1/02 ,  B81C2201/0121 ,  B81C2201/0123 ,  B81C2201/0126 ,  H01L21/02024 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/461

Abstract: A process for the manufacture of semiconductor devices comprising the chemical-mechanical polishing of a substrate or layer containing at least one III-V material in the presence of a chemical-mechanical polishing composition (Q1) comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) at least one amphiphilic non-ionic surfactant having (b1) at least one hydrophobic group; and (b2) at least one hydrophilic group selected from the group consisting of polyoxyalkylene groups comprising (b22) oxyalkylene monomer units other than oxyethylene monomer units; and (M) an aqueous medium.

Abstract translation: 一种用于制造半导体器件的方法，包括在化学机械抛光组合物（Q1）的存在下对包含至少一种III-V材料的基底或层进行化学机械抛光，所述化学机械抛光组合物包含（A）无机颗粒，有机颗粒， 或其混合物或复合物，（B）至少一种具有（b1）至少一个疏水基团的两亲性非离子表面活性剂; 和（b2）至少一种选自包含（b22）氧化烯单体单元以外的氧化烯单体单元的聚氧化烯基的亲水基团; 和（M）水性介质。

公开(公告)号：US06846746B2

公开(公告)日：2005-01-25

申请号：US10137543

申请日：2002-05-01

Applicant: Michael Rattner ,  Jeffrey D. Chinn

Inventor： Michael Rattner ,  Jeffrey D. Chinn

IPC: B81C1/00 ,  H01L21/3065 ,  H01L21/302

CPC classification number: B81C1/00611 ,  B81B2203/033 ,  B81C2201/0126 ,  B81C2201/0178 ,  H01L21/3065 ,  H01L21/30655

Abstract: Disclosed herein is a method of smoothing a trench sidewall after a deep trench silicon etch process which minimizes sidewall scalloping present after the silicon trench etch. The method comprises exposing the silicon trench sidewall to a plasma generated from a fluorine-containing gas, at a process chamber pressure within the range of about 1 mTorr to about 30 mTorr, for a time period within the range of about 10 seconds to about 600 seconds. A substrate bias voltage within the range of about −10 V to about −40 V is applied during the performance of the post-etch treatment method of the invention.

Abstract translation: 这里公开了一种在深沟槽硅蚀刻工艺之后平滑沟槽侧壁的方法，其最小化在硅沟槽蚀刻之后存在的侧壁扇形。 该方法包括将硅沟槽侧壁暴露于在约1mTorr至约30mTorr范围内的处理室压力下从含氟气体产生的等离子体，时间范围为约10秒至约600 秒。 在本发明的蚀刻后处理方法的执行期间，施加约-10V至约-40V范围内的衬底偏置电压。

公开(公告)号：US20080119051A1

公开(公告)日：2008-05-22

申请号：US11562443

申请日：2006-11-22

Applicant: Suryadevara V. Babu ,  Anita Natarajan ,  Sharath Hegde

Inventor： Suryadevara V. Babu ,  Anita Natarajan ,  Sharath Hegde

IPC: H01L21/304

CPC classification number: H01L21/3212 ,  B81C1/00595 ,  B81C1/00611 ,  B81C2201/0104 ,  B81C2201/0126 ,  C09G1/02 ,  C09K3/1463

Abstract: A method of removing polysilicon in preference to silicon dioxide and/or silicon nitride by chemical mechanical polishing. The method removes polysilicon from a surface at a high removal rate while maintaining a high selectivity of polysilicon to silicon dioxide and/or a polysilicon to silicon nitride. The method is particularly suitable for use in the fabrication of MEMS devices.

Abstract translation: 通过化学机械抛光优选去除二氧化硅和/或氮化硅的多晶硅的方法。 该方法以高去除率从表面去除多晶硅，同时保持多晶硅对二氧化硅和/或多晶硅与氮化硅的高选择性。 该方法特别适用于MEMS器件的制造。

公开(公告)号：US07259080B2

公开(公告)日：2007-08-21

申请号：US10526962

申请日：2003-08-22

Applicant: Hans-Joachim Quenzer ,  Arne-Veit Schulz ,  Peter Merz

Inventor： Hans-Joachim Quenzer ,  Arne-Veit Schulz ,  Peter Merz

IPC: H01L21/46 ,  H01L21/30 ,  H01L21/324 ,  H01L21/50 ,  H01L21/48

CPC classification number: B81C1/00611 ,  B81C2201/0126 ,  C03B19/02 ,  C03B23/02

Abstract: The invented method is distinguished by a combination of the following method steps: provision of a semiconductor planar substrate composed of a semiconductor material, reduction of the thickness of the semiconductor planar substrate inside at least one surface region of the semiconductor planar substrate in order to form a raised surface region in relation to the surface planar region of reduced thickness, structuring the raised surface region of the semiconductor planar substrate by means of local mechanical removal of material in order to place impressions inside the raised surface regions, joining the structured surface of the semiconductor planar substrate with the glasslike planar substrate in such a manner that the glasslike planar substrate at least partially covers the surface planar region of reduced thickness, tempering the joined planar substrates in such a manner that in a first tempering phase, which is conducted under vacuum conditions, the glasslike planar substrate covering the surface region of reduced thickness forms a fluid-tight bond with the surface region of reduced thickness, with the planar substrate covering the impressions in a fluid-tight manner under vacuum conditions, and that in a second tempering phase, at least partial areas of the glasslike material flow into the impressions of the structured surface of the semiconductor planar substrate.

Abstract translation: 本发明的方法通过以下方法步骤的组合来区分：提供由半导体材料构成的半导体平面基板，减小半导体平面基板的至少一个表面区域内的半导体平面基板的厚度，以形成 相对于减小厚度的表面平面区域的凸起表面区域，通过局部机械去除材料构造半导体平面基板的凸起表面区域，以将印模放置在凸起表面区域内，将结构化表面 具有玻璃状平面基板的半导体平面基板，使得玻璃状平面基板至少部分地覆盖厚度减小的表面平面区域，以这样的方式回火接合的平面基板，使得在真空下进行的第一回火阶段 条件，玻璃状平面基板cov 减小厚度的表面区域形成与减小厚度的表面区域的流体密封结合，其中平面基板在真空条件下以流体密封的方式覆盖印模，并且在第二回火阶段中，至少部分区域 的玻璃状材料流入半导体平面基板的结构化表面的印模中。

公开(公告)号：US20060110893A1

公开(公告)日：2006-05-25

申请号：US10526962

申请日：2003-08-22

Applicant: Hans-Joachim Quenzer ,  Arne-Veit Schulz ,  Peter Merz

Inventor： Hans-Joachim Quenzer ,  Arne-Veit Schulz ,  Peter Merz

IPC: H01L21/30

CPC classification number: B81C1/00611 ,  B81C2201/0126 ,  C03B19/02 ,  C03B23/02

Abstract: The invented method is distinguished by a combination of the following method steps: provision of a semiconductor planar substrate composed of a semiconductor material, reduction of the thickness of the semiconductor planar substrate inside at least one surface region of the semiconductor planar substrate in order to form a raised surface region in relation to the surface planar region of reduced thickness, structuring the raised surface region of the semiconductor planar substrate by means of local mechanical removal of material in order to place impressions inside the raised surface regions, joining the structured surface of the semiconductor planar substrate with the glasslike planar substrate in such a manner that the glasslike planar substrate at least partially covers the surface planar region of reduced thickness, tempering the joined planar substrates in such a manner that in a first tempering phase, which is conducted under vacuum conditions, the glasslike planar substrate covering the surface region of reduced thickness forms a fluid-tight bond with the surface region of reduced thickness, with the planar substrate covering the impressions in a fluid-tight manner under vacuum conditions, and that in a second tempering phase, at least partial areas of the glasslike material flow into the impressions of the structured surface of the semiconductor planar substrate.

Abstract translation: 本发明的方法通过以下方法步骤的组合来区分：提供由半导体材料构成的半导体平面基板，减小半导体平面基板的至少一个表面区域内的半导体平面基板的厚度，以形成 相对于减小厚度的表面平面区域的凸起表面区域，通过局部机械去除材料构造半导体平面基板的凸起表面区域，以将印模放置在凸起表面区域内，将结构化表面 具有玻璃状平面基板的半导体平面基板，使得玻璃状平面基板至少部分地覆盖厚度减小的表面平面区域，以这样的方式回火接合的平面基板，使得在真空下进行的第一回火阶段 条件，玻璃状平面基板cov 减小厚度的表面区域形成与减小厚度的表面区域的流体密封结合，其中平面基板在真空条件下以流体密封的方式覆盖印模，并且在第二回火阶段中，至少部分区域 的玻璃状材料流入半导体平面基板的结构化表面的印模中。

公开(公告)号：US06472235B1

公开(公告)日：2002-10-29

申请号：US09886881

申请日：2001-06-21

Applicant: Kuang-Peng Lin ,  Hung-Jen Tsai ,  Hsien-Tsong Liu

Inventor： Kuang-Peng Lin ,  Hung-Jen Tsai ,  Hsien-Tsong Liu

IPC: H01L2166

CPC classification number: B81C99/0035 ,  B81C1/00611 ,  B81C2201/0126 ,  Y10S438/959

Abstract: A method and an apparatus for preparing a backside-ground wafer for testing are described. The method includes the steps of first providing a calibration wafer that has a pattern formed on a top surface of an insulating material such as oxide or nitride. Three droplets of water are applied with each droplet sufficiently apart from the other droplets on the top surface of the calibration wafer. A backside-ground wafer that has a ground backside and a front side to be tested is then mated to the calibration wafer by mating the ground backside to the top surface of the calibration wafer with water droplets therein-between forming a bond by capillary reaction in-between the oxide pattern on the calibration wafer. The apparatus for mounting a backside-ground wafer to a calibration wafer consists of a slanted block having a top surface with a slant angle between about 10° and about 30°.

Abstract translation: 描述了用于制备用于测试的背面晶片的方法和装置。 该方法包括以下步骤：首先提供具有形成在诸如氧化物或氮化物的绝缘材料的顶表面上的图案的校准晶片。 每个液滴与校准晶片的顶表面上的其它液滴充分分开地施加三滴水。 将具有接地背面和待测试的前侧的背面晶片然后通过将地面背面与校准晶片的顶表面配合而与校准晶片配合，并通过毛细管反应形成键 - 在校准晶片上的氧化物图案之间。 用于将背面晶片安装到校准晶片的装置包括具有在大约10°至大约30°之间的倾斜角的顶表面的倾斜块。