公开(公告)号：US20180263117A1

公开(公告)日：2018-09-13

申请号：US15810800

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravindranath V. Mahajan ,  James C. Matayabas, JR. ,  Johanna M. Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H01L23/00

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US09999130B2

公开(公告)日：2018-06-12

申请号：US15258330

申请日：2016-09-07

Applicant: Hisense Broadband Multimedia Technologies Co., Ltd.

Inventor： Wei Zhao ,  Wei Cui ,  Lin Yu

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/18 ,  H05K1/0298 ,  H05K1/117 ,  H05K3/3452 ,  H05K2201/0137 ,  H05K2201/10121

Abstract: The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive wirings and electro-conductive contact sheet group both laid on the surface of the substrate, where the substrate is overlaid with solder resist, and the solder resist has no contact with the electro-conductive contact sheet group.

公开(公告)号：US20170228055A1

公开(公告)日：2017-08-10

申请号：US15494800

申请日：2017-04-24

Applicant: Sinovia Technologies

Inventor： Whitney GAYNOR ,  George BURKHARD

IPC: G06F3/041 ,  G03F1/24 ,  H01B5/14 ,  B05D3/00 ,  H01B13/00 ,  H01B1/22

CPC classification number: G06F3/041 ,  B05D3/007 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F7/0002 ,  G03F7/0047 ,  G03F7/038 ,  G03F7/0388 ,  G03F7/161 ,  G06F3/044 ,  G06F2203/04103 ,  H01B1/22 ,  H01B5/14 ,  H01B13/0013 ,  H01L51/444 ,  H01L51/5203 ,  H05K1/0271 ,  H05K1/0274 ,  H05K1/036 ,  H05K1/09 ,  H05K3/103 ,  H05K2201/0108 ,  H05K2201/0137 ,  H05K2203/10 ,  Y10T428/24355 ,  Y10T442/188 ,  Y10T442/191

Abstract: A method of fabricating a composite conductive film is provided. The method includes providing, as a matrix, a layer of cross-linkable polymer, where the cross-linkable polymer is in a non-cross-linked state. The method further includes introducing inorganic nanowires upon a surface of the layer of cross-linkable polymer. The inorganic nanowires are, in isolated form, characterized by a first conductivity stability temperature. The method further includes embedding at least some of the inorganic nanowires into the layer of cross-linkable polymer to form an inorganic mesh, thereby forming the composite conductive film. The method further includes cross-linking the polymer within a surface portion of the composite conductive film. Cross-linking the polymer within the surface portion of the composite conductive film results in the surface portion having a second conductivity stability temperature that is greater than the first conductivity stability temperature.

公开(公告)号：US09652055B2

公开(公告)日：2017-05-16

申请号：US14142036

申请日：2013-12-27

Applicant: APPLIED MATERIALS, INC.

Inventor： Neil Morrison ,  Thomas Deppisch ,  Hans-Georg Lotz

IPC: H05K1/03 ,  G06F3/044 ,  G06F3/0354 ,  G06F3/041 ,  H05K1/02

CPC classification number: G06F3/03547 ,  G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  H05K1/0274 ,  H05K1/0306 ,  H05K2201/0137 ,  H05K2201/0145

Abstract: A layer stack for a touch panel is described. The layer stack includes a substrate including a polymer for depositing one or more layers on the substrate; a patterned transparent conductive oxide (TCO) layer provided over the substrate, which comprises areas of TCO and gaps between the areas of TCO; a first dielectric material provided in the gaps of the patterned TCO layer and a dielectric layer being deposited directly on the TCO areas of the TCO layer and directly on the first dielectric material. Further, a touch panel including a layer stack and a method for forming a layer stack for a touch panel is described.

公开(公告)号：US20150156887A1

公开(公告)日：2015-06-04

申请号：US14209143

申请日：2014-03-13

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Ji Sung Cho ,  Toshiko Yokota ,  Makoto Dobashi ,  Jin Gu Kim ,  Ichiro Ogura ,  Je Hong Kyoung

IPC: H05K3/02 ,  H05K1/09

CPC classification number: H05K3/022 ,  H05K1/09 ,  H05K3/16 ,  H05K2201/0137 ,  H05K2201/032 ,  H05K2201/0338 ,  Y10T428/12569

Abstract: Disclosed herein are a method of forming an amorphous alloy film and a printed wiring board manufactured by the same. The amorphous alloy film may be formed on a copper foil as one of rust-proofing treatment methods of the copper foil to thereby simultaneously show and improve corrosion-resistance and conductivity, and the amorphous alloy film may be formed by the sputtering deposition method, such that high melting point materials may be manufactured as a thin film at a relatively low temperature and the amorphous alloy film having strong adhesion strength with a substrate may be obtained.

Abstract translation: 本文公开了形成非晶合金膜的方法和由其制造的印刷线路板。 非晶合金膜可以形成在铜箔上作为铜箔的防锈处理方法之一，从而同时显示并提高耐腐蚀性和导电性，并且非晶合金膜可以通过溅射沉积法形成，例如 可以在相对低的温度下制造高熔点材料作为薄膜，并且可以获得与基板具有强粘合强度的非晶态合金膜。

公开(公告)号：US20150109748A1

公开(公告)日：2015-04-23

申请号：US14360906

申请日：2011-11-29

Applicant: Zhongyao Yu ,  Xia Zhang

Inventor： Zhongyao Yu ,  Xia Zhang

IPC: H05K1/18 ,  H05K3/46 ,  H01L21/78 ,  H05K1/11 ,  H01L25/00 ,  H01L25/16

CPC classification number: H05K1/188 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24135 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/12042 ,  H05K1/115 ,  H05K1/185 ,  H05K3/46 ,  H05K3/4652 ,  H05K2201/0137 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/09509 ,  H01L2924/00

Abstract: An active chip package substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip, embedded in the core board and having an active surface facing toward a lower surface of the core board, the upper active chip being an active bare chip; and at least one lower active chip, embedded in the core board and having an active surface facing toward an upper surface of the core board, the lower active chip being an active bare chip.

Abstract translation: 一种有源芯片封装基板及其制备方法。 有源芯片封装基板包括：芯板; 至少一个上有源芯片，嵌入在所述芯板中并且具有面向所述芯板的下表面的有源表面，所述上有源芯片是有源裸芯片; 以及至少一个下部有源芯片，嵌入在所述芯板中并且具有面向所述芯板的上表面的有源表面，所述下部有源芯片是有源裸芯片。

公开(公告)号：US20150047882A1

公开(公告)日：2015-02-19

申请号：US14380981

申请日：2013-02-26

Applicant: APPLIED NANOTECH HOLDINGS, INC.

Inventor： Nan Jiang ,  Zvi Yaniv

IPC: H05K1/05 ,  H05K1/02 ,  H05K3/12 ,  H05K1/09

CPC classification number: H05K1/053 ,  C04B41/009 ,  C04B41/52 ,  C04B41/90 ,  C04B2111/00844 ,  H01L23/373 ,  H01L2924/0002 ,  H05K1/0284 ,  H05K1/09 ,  H05K1/181 ,  H05K3/12 ,  H05K2201/0104 ,  H05K2201/0137 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/06 ,  H05K2201/10106 ,  H01L2924/00 ,  C04B35/522 ,  C04B41/4539 ,  C04B41/5001 ,  C04B41/5031 ,  C04B41/5089 ,  C04B41/5059 ,  C04B41/5092 ,  C04B41/522 ,  C04B41/5063 ,  C04B41/5064 ,  C04B41/4535 ,  C04B41/4572 ,  C04B41/5127

Abstract: Different kinds of printing pastes or inks are utilized in various combinations to develop multiple ceramic dielectric layers on graphitic substrates in order to create effective dielectric ceramic layers that combine good adhesion to both graphitic substrates and printed copper traces, and strong insulating capability. The pastes or inks may comprise a high thermal conductivity powder.

Abstract translation: 不同种类的印刷浆料或油墨被用于各种组合以在石墨基材上形成多个陶瓷电介质层，以便产生有效的介电陶瓷层，其与石墨基材和印刷的铜迹线具有良好的粘合性，并具有很强的绝缘性能。 糊剂或油墨可以包含高导热性粉末。

公开(公告)号：US20150034373A1

公开(公告)日：2015-02-05

申请号：US14379420

申请日：2013-02-13

Applicant: Yoshiki Nakashima ,  Masahiro Kubo ,  Akinobu Shibuya

Inventor： Yoshiki Nakashima ,  Masahiro Kubo ,  Akinobu Shibuya

IPC: H05K3/12 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K3/1275 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/4685 ,  H05K2201/0129 ,  H05K2201/0137 ,  H05K2203/0278 ,  Y10T29/49155

Abstract: A wiring structure includes a substrate, a convexoconcave absorption layer including a convexoconcave portion on the substrate, a conductive layer pattern on at least a concave portion of the convexoconcave absorption layer, and an insulating layer pattern over the conductive layer pattern and the convexoconcave absorption layer, on at least the concave portion. This configuration provides a wiring structure and a manufacturing method thereof which enable to form fine multilayer wiring using microcontact printing or the like.

Abstract translation: 布线结构包括基板，在基板上包括凸凹部的凸凹陷波吸收层，凹凸吸收层的至少凹部的导电层图案，以及导电层图案和凹凸吸收层之上的绝缘层图案 至少在凹部上。 这种结构提供了使用微接触印刷等形成精细多层布线的布线结构及其制造方法。

公开(公告)号：US20180270954A1

公开(公告)日：2018-09-20

申请号：US15982240

申请日：2018-05-17

Applicant: HISENSE BROADBAND MULIMEDIA TECHNOLOGIES CO. LTD. ,  HISENSE USA CORORATION ,  HISENSE INTERNATIONAL CO., LTD.

Inventor： Wei ZHAO ,  Wei CUI ,  Lin YU

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/18 ,  H05K1/0298 ,  H05K1/117 ,  H05K3/3452 ,  H05K2201/0137 ,  H05K2201/10121

Abstract: The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive contact sheet group positioned on the surface of the substrate, where a part of the substrate is overlaid with solder resist, and there is a gap between the solder resist and the electro-conductive contact sheet group.

公开(公告)号：US09942989B2

公开(公告)日：2018-04-10

申请号：US14312222

申请日：2014-06-23

Applicant: ILLINOIS TOOL WORKS, INC.

Inventor： Hongchuan Liao ,  Chris Benson ,  Yong Liang ,  Tom Carlson

IPC: H05K7/00 ,  H05K1/18 ,  B32B27/08 ,  B32B27/20 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36

CPC classification number: H05K1/185 ,  B32B27/08 ,  B32B27/20 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B27/365 ,  B32B2250/24 ,  B32B2250/40 ,  B32B2262/106 ,  B32B2264/02 ,  B32B2264/102 ,  B32B2264/105 ,  B32B2264/107 ,  B32B2264/108 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2307/212 ,  B32B2307/302 ,  B32B2457/04 ,  H05K2201/0137 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0183 ,  Y10T428/31507 ,  Y10T428/31681 ,  Y10T428/31692 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31728 ,  Y10T428/31736 ,  Y10T428/31757 ,  Y10T428/31786 ,  Y10T428/31797 ,  Y10T428/31913

Abstract: The present invention provides an insulation film and a method for making the insulation film, comprising a film upper layer and a film lower layer, wherein both of the film upper layer and film lower layer are made of a heat conduction plastics material, the heat conduction plastics material contains a heat conduction additive; and a film intermediate layer located between the film upper layer and the film lower layer. The film intermediate layer is made of a heat conduction plastics material, and the heat conduction plastics material contains a conductive additive An upper surface of the film intermediate layer is bound together with a lower surface of the film upper layer, and a lower surface of the film intermediate layer is bound together with an upper surface of the film lower layer.